CY7C1484BV33-250BZXC

CY7C1484BV33-250BZXC Datasheet

CY7C1484BV33

Part	Datasheet
CY7C1484BV33-250BZXC	CY7C1484BV33-250BZXC (pdf)

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CY7C1484BV33 72-Mbit 2 M x 36 Pipelined DCD Sync SRAM 72-Mbit 2 M x 36 Pipelined DCD Sync SRAM • Supports bus operation up to 250 MHz • Available speed grade is 250 MHz • Registered inputs and outputs for pipelined operation • Optimal for performance double cycle deselect • Depth expansion without wait state • V core power supply VDD • V and V I/O operation • Fast clock to output times ns for 250 MHz device • Provide high performance 3-1-1-1 access rate • User selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self timed writes • Asynchronous output enable • CY7C1484BV33 available in Pb-free 165-ball FBGA package • IEEE JTAG compatible boundary scan • “ZZ” sleep mode option Functional Description The CY7C1484BV33 SRAM integrates 2 M x 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable CE1 , depth expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BWX, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle. This part supports byte write operations see Pin Definitions on page 5 and Truth Table on page 8 for more information . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register, which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1484BV33 operates from a V core power supply while all outputs operate with a V or a V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz Unit • San Jose, CA 95134-1709 • 408-943-2600 CY7C1484BV33 Logic Block Diagram CY7C1484BV33 A 0,A1,A MODE ADV CLK ADSC ADSP BW A BWE GW CE 1 CE 2 CE 3 OE ADDRESS REGISTER 2 A[1:0] BURST Q1 COUNTER AND LOGIC DQ D,DQP D BYTE WRITE REGISTER DQ c,DQP C BYTE WRITE REGISTER DQ B,DQP B BYTE WRITE REGISTER DQ A, DQP A BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE DQ D,DQP D BYTE WRITE DRIVER DQ c,DQP C BYTE WRITE DRIVER DQ B,DQP B BYTE WRITE DRIVER DQ A, DQP A BYTE TAP DC Electrical Characteristics and Operating Conditions 15 Identification Register Definitions 16 Scan Register Sizes 16 Identification Codes 16 Boundary Scan Exit Order 17 Maximum Ratings 18 Operating Range 18 Electrical Characteristics 18 Capacitance 19 Thermal Resistance 19 AC Test Loads and Waveforms 20 Switching Characteristics 21 Switching Waveforms 22 Ordering Information 26 Ordering Code Definitions 26 Package Diagrams 27 Acronyms 28 Document Conventions 28 Units of Measure 28 Document History Page 29 Sales, Solutions, and Legal Information 30 Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30 Page 3 of 30 CY7C1484BV33 Pin Configurations Figure 165-ball FBGA 15 x 17 x mm pinout CY7C1484BV33 2 M x 36 A NC/288M A B NC/144M A DQPC DQPD R MODE CE1 CE2 VDDQ NC VDDQ BWC BWD VSS VDD VSS BWB BWA VSS NC CE3 CLK GW VSS NC ADSC VSS VDD VSS ADSP VDDQ NC VDDQ A NC/576M NC/1G DQB NC DQPB DQB DQB ZZ DQA NC DQA DQPA Page 4 of 30 CY7C1484BV33 Pin Definitions Pin Name A0, A1, A Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the 2-bit counter. BWA, BWB BWC, BWD GW Input- Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK. Input- Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write Synchronous is conducted ALL bytes are written, regardless of the values on BWX and BWE . Input- Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. Input- Clock Input. Capture all synchronous inputs to the device. Also used to increment the burst counter Clock when ADV is asserted LOW during a burst operation. Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 250 CY7C1484BV33-250BZXC 51-85165 165-ball FBGA 15 x 17 x mm Pb-free Commercial Ordering Code Definitions CY 7 C 1484 B V33 - 250 BZ X C Temperature range C = Commercial = 0 °C to +70 °C X = Pb-free Package Type BZ = 165-ball FBGA Speed Grade 250 MHz V33 = V Process Technology B errata fix PCN084636 Part Identifier 1484 = DCD, 2 M x 36 72 Mb Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Page 26 of 30 CY7C1484BV33 Package Diagrams Figure 165-ball FBGA 15 x 17 x mm Ball Diameter Package Outline, 51-85165 51-85165 *D Page 27 of 30 Acronyms Acronym chip enable CMOS complementary metal-oxide-semiconductor electronic industries alliance FBGA fine-pitch ball grid array input/output JEDEC joint electron devices engineering council JTAG joint test action group least significant bit most significant bit output enable SRAM static random access memory test access port test clock test data-in test data-out test mode select transistor-transistor logic CY7C1484BV33 Document Conventions Units of Measure Symbol °C MHz µA mA mm ms mV ns % pF V W Unit of Measure degree Celsius megahertz microampere milliampere millimeter millisecond millivolt nanosecond ohm percent picofarad volt watt Page 28 of 30 CY7C1484BV33 Document History Page Document Title CY7C1484BV33, 72-Mbit 2 M x 36 Pipelined DCD Sync SRAM Document Number 001-75351

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CY7C1484BV33
72-Mbit 2 M x 36 Pipelined DCD Sync SRAM
72-Mbit 2 M x 36 Pipelined DCD Sync SRAM
• Supports bus operation up to 250 MHz
• Available speed grade is 250 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance double cycle deselect
• Depth expansion without wait state
• V core power supply VDD
• V and V I/O operation
• Fast clock to output times
ns for 250 MHz device
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• CY7C1484BV33 available in Pb-free 165-ball FBGA package
• IEEE JTAG compatible boundary scan
• “ZZ” sleep mode option

Functional Description

The CY7C1484BV33 SRAM integrates 2 M x 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable CE1 , depth expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BWX, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle. This part supports byte write operations see Pin Definitions on page 5 and Truth Table on page 8 for more information . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register, which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1484BV33 operates from a V core power supply while all outputs operate with a V or a V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible.

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
250 MHz Unit
• San Jose, CA 95134-1709
• 408-943-2600

CY7C1484BV33

Logic Block Diagram CY7C1484BV33

A 0,A1,A MODE

ADV CLK

ADSC ADSP

BW A BWE GW

CE 1 CE 2 CE 3 OE

ADDRESS REGISTER
2 A[1:0]

BURST Q1

COUNTER AND

LOGIC

DQ D,DQP D BYTE

WRITE REGISTER

DQ c,DQP C BYTE

WRITE REGISTER

DQ B,DQP B BYTE

WRITE REGISTER

DQ A, DQP A BYTE

WRITE REGISTER

ENABLE REGISTER

PIPELINED ENABLE

DQ D,DQP D BYTE

WRITE DRIVER

DQ c,DQP C BYTE

WRITE DRIVER

DQ B,DQP B BYTE

WRITE DRIVER

DQ A, DQP A BYTE
TAP DC Electrical Characteristics and Operating Conditions 15 Identification Register Definitions 16 Scan Register Sizes 16 Identification Codes 16 Boundary Scan Exit Order 17 Maximum Ratings 18 Operating Range 18 Electrical Characteristics 18 Capacitance 19 Thermal Resistance 19 AC Test Loads and Waveforms 20 Switching Characteristics 21 Switching Waveforms 22 Ordering Information 26
Ordering Code Definitions 26 Package Diagrams 27 Acronyms 28 Document Conventions 28

Units of Measure 28 Document History Page 29 Sales, Solutions, and Legal Information 30

Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30

Page 3 of 30

CY7C1484BV33

Pin Configurations

Figure 165-ball FBGA 15 x 17 x mm pinout CY7C1484BV33 2 M x 36

A NC/288M A

B NC/144M A

DQPC

DQPD

R MODE

CE1 CE2 VDDQ NC VDDQ

BWC BWD VSS VDD VSS

BWB BWA VSS NC

CE3 CLK

GW VSS NC

ADSC

VSS VDD VSS

ADSP VDDQ

NC VDDQ

A NC/576M

NC/1G

DQB NC

DQPB DQB

DQB ZZ

DQA NC

DQA DQPA

Page 4 of 30

CY7C1484BV33

Pin Definitions

Pin Name

A0, A1, A

Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the 2-bit
counter.

BWA, BWB BWC, BWD GW

Input- Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK.

Input- Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write Synchronous is conducted ALL bytes are written, regardless of the values on BWX and BWE .

Input- Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write.

Input- Clock Input. Capture all synchronous inputs to the device. Also used to increment the burst counter

Clock when ADV is asserted LOW during a burst operation.
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
250 CY7C1484BV33-250BZXC
51-85165 165-ball FBGA 15 x 17 x mm Pb-free

Commercial
Ordering Code Definitions CY 7 C 1484 B V33 - 250 BZ X C

Temperature range C = Commercial = 0 °C to +70 °C X = Pb-free Package Type BZ = 165-ball FBGA Speed Grade 250 MHz V33 = V Process Technology B errata fix PCN084636 Part Identifier 1484 = DCD, 2 M x 36 72 Mb Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress

Page 26 of 30

CY7C1484BV33

Package Diagrams

Figure 165-ball FBGA 15 x 17 x mm Ball Diameter Package Outline, 51-85165
51-85165 *D

Page 27 of 30

Acronyms

Acronym
chip enable

CMOS
complementary metal-oxide-semiconductor
electronic industries alliance

FBGA
fine-pitch ball grid array
input/output

JEDEC joint electron devices engineering council

JTAG
joint test action group
least significant bit
most significant bit
output enable

SRAM
static random access memory
test access port
test clock
test data-in
test data-out
test mode select
transistor-transistor logic

CY7C1484BV33

Document Conventions

Units of Measure

Symbol °C MHz µA mA mm ms mV ns
% pF V W

Unit of Measure degree Celsius megahertz microampere milliampere millimeter millisecond millivolt nanosecond ohm percent picofarad volt watt

Page 28 of 30

CY7C1484BV33

Document History Page

Document Title CY7C1484BV33, 72-Mbit 2 M x 36 Pipelined DCD Sync SRAM Document Number 001-75351

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1484BV33-250BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1484BV33-250BZXC 508049