CY7C1480V33-250BZI

CY7C1480V33-250BZI Datasheet

CY7C1480V33 CY7C1482V33 CY7C1486V33

Part	Datasheet
CY7C1480V33-250BZI	CY7C1480V33-250BZI (pdf)

Related Parts	Information
CY7C1480V33-167BZI	CY7C1480V33-167BZI

PDF Datasheet Preview
CY7C1480V33 CY7C1482V33 CY7C1486V33 72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined Sync SRAM Functional Description[1] • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times ns for 250-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • CY7C1480V33, CY7C1482V33 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1486V33 available in lead-free and non-lead-free 209 ball FBGA package • IEEE JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BWX, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz 500 120 200 MHz 500 120 167 MHz 450 120 Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Unit ns mA Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1480V33 CY7C1482V33 CY7C1486V33 Logic Block Diagram CY7C1480V33 2M x 36 A0, A1, A MODE ADV CLK ADSC ADSP BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A[1:0] BURST COUNTER CLR AND Q0 LOGIC DQD ,DQPD BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 167 CY7C1480V33-167AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1482V33-167AXC CY7C1480V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1482V33-167BZC CY7C1480V33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free CY7C1482V33-167BZXC CY7C1486V33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1486V33-167BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free CY7C1480V33-167AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free lndustrial CY7C1482V33-167AXI CY7C1480V33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1482V33-167BZI CY7C1480V33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free CY7C1482V33-167BZXI CY7C1486V33-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1486V33-167BGXI 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free 200 CY7C1480V33-200AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1482V33-200AXC CY7C1480V33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1482V33-200BZC CY7C1480V33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free CY7C1482V33-200BZXC CY7C1486V33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1486V33-200BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free CY7C1480V33-200AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free lndustrial CY7C1482V33-200AXI CY7C1480V33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1482V33-200BZI CY7C1480V33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free CY7C1482V33-200BZXI Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 250 CY7C1480V33-250AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1482V33-250AXC CY7C1480V33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1482V33-250BZC CY7C1480V33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free CY7C1482V33-250BZXC CY7C1486V33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1486V33-250BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free CY7C1480V33-250AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial CY7C1482V33-250AXI CY7C1480V33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1482V33-250BZI CY7C1480V33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free CY7C1482V33-250BZXI CY7C1486V33-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1486V33-250BGXI 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free Page 27 of 31 [+] Feedback CY7C1480V33 CY7C1482V33 CY7C1486V33 Package Diagrams 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm 51-85050 100 1 81 80 R MIN. MAX. GAUGE PLANE 0° -7° REF. 30 31 0° MIN. R MIN. MAX. MIN. DETAIL A TYP. 51 50 Updated Ordering Information Changed Advanced Information to Preliminary 233368 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 250-MHz speed grade offering and included 225-MHz speed bin Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering 299452 See ECN SYT Removed 225-MHz offering and included 250-MHz speed bin Changed tCYC from ns to ns for 250-MHz Speed Bin Changed ΘJA from to °C/W and ΘJC from to °C/W for 100 TQFP Package on Page # 20 Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA Packages Added comment of ‘Lead-free BG packages availability’ below the Ordering Information 323080 See ECN PCI Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection Guide Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Added Truth Table and Note# 7 for CY7C1486V33 on page# 11 Added Industrial Operating Range Modified VOL, VOH test conditions Removed comment of ‘Lead-free BG packages availability’ below the Ordering Information Updated Ordering Information Table 416193 See ECN NXR Converted Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of IX from Input Load Current to Input Leakage Current on page# 19 Changed the IX current values of MODE on page # 19 from -5 µA and 30 µA to -30 µA and 5 µA Changed the IX current values of ZZ on page # 19 from -30 µA and 5 µA to -5 µA and 30 µA Changed VIH < VDD to VIH < VDD on page # 19 Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table 470723 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH,tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table 486690 See ECN VKN Corrected the typo in the 209-Ball FBGA pinout. Corrected the ball name H9 to VSS from VSSQ . Page 31 of 31 [+] Feedback

PDF Datasheet Preview

CY7C1480V33 CY7C1482V33 CY7C1486V33
72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined Sync SRAM

Functional Description[1]
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
ns for 250-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• CY7C1480V33, CY7C1482V33 available in

JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1486V33 available in lead-free and non-lead-free 209 ball FBGA package
• IEEE JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option

The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BWX, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
250 MHz 500 120
200 MHz 500 120
167 MHz 450 120

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on

Unit ns mA

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1480V33 CY7C1482V33 CY7C1486V33

Logic Block Diagram CY7C1480V33 2M x 36

A0, A1, A

MODE ADV CLK

ADSC ADSP

BWA BWE GW

CE1 CE2 CE3 OE

ADDRESS REGISTER

A[1:0]

BURST COUNTER CLR AND Q0

LOGIC

DQD ,DQPD BYTE

WRITE REGISTER

DQC ,DQPC BYTE

WRITE REGISTER

DQB ,DQPB BYTE

WRITE REGISTER

DQA ,DQPA BYTE

WRITE REGISTER

ENABLE REGISTER

PIPELINED ENABLE
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
167 CY7C1480V33-167AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1482V33-167AXC

CY7C1480V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm

CY7C1482V33-167BZC

CY7C1480V33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free

CY7C1482V33-167BZXC

CY7C1486V33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1486V33-167BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

CY7C1480V33-167AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
lndustrial

CY7C1482V33-167AXI

CY7C1480V33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm

CY7C1482V33-167BZI

CY7C1480V33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free

CY7C1482V33-167BZXI

CY7C1486V33-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1486V33-167BGXI
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free
200 CY7C1480V33-200AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1482V33-200AXC

CY7C1480V33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm

CY7C1482V33-200BZC

CY7C1480V33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free

CY7C1482V33-200BZXC

CY7C1486V33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1486V33-200BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

CY7C1480V33-200AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
lndustrial

CY7C1482V33-200AXI

CY7C1480V33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm

CY7C1482V33-200BZI

CY7C1480V33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free

CY7C1482V33-200BZXI
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
250 CY7C1480V33-250AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1482V33-250AXC

CY7C1480V33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm

CY7C1482V33-250BZC

CY7C1480V33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free

CY7C1482V33-250BZXC

CY7C1486V33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1486V33-250BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

CY7C1480V33-250AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Industrial

CY7C1482V33-250AXI

CY7C1480V33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm

CY7C1482V33-250BZI

CY7C1480V33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Lead-Free

CY7C1482V33-250BZXI

CY7C1486V33-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1486V33-250BGXI
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

Page 27 of 31 [+] Feedback

CY7C1480V33 CY7C1482V33 CY7C1486V33

Package Diagrams
100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm 51-85050
100 1
81 80

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
30 31
0° MIN.

R MIN. MAX.

MIN.

DETAIL A

TYP.
51 50
Updated Ordering Information

Changed Advanced Information to Preliminary
233368 See ECN NJY Changed timing diagrams

Changed logic block diagrams

Modified Functional Description

Modified “Functional Overview” section

Added boundary scan order for all packages

Included thermal numbers and capacitance values for all packages

Included IDD and ISB values

Removed 250-MHz speed grade offering and included 225-MHz speed bin

Changed package outline for 165FBGA package and 209-ball BGA package

Removed 119-BGA package offering
299452 See ECN SYT Removed 225-MHz offering and included 250-MHz speed bin

Changed tCYC from ns to ns for 250-MHz Speed Bin Changed ΘJA from to °C/W and ΘJC from to °C/W for 100 TQFP Package on Page # 20

Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA

Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering

Information
323080 See ECN

PCI Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection

Guide

Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard

Added Address Expansion pins in the Pin Definitions Table

Added Truth Table and Note# 7 for CY7C1486V33 on page# 11

Added Industrial Operating Range

Modified VOL, VOH test conditions Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
416193 See ECN NXR Converted Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Changed the description of IX from Input Load Current to Input Leakage Current on page# 19

Changed the IX current values of MODE on page # 19 from -5 µA and 30 µA to -30 µA and 5 µA

Changed the IX current values of ZZ on page # 19 from -30 µA and 5 µA to -5 µA and 30 µA
Changed VIH < VDD to VIH < VDD on page # 19 Replaced Package Name column with Package Diagram in the Ordering

Information table
Updated the Ordering Information Table
470723 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

Changed tTH,tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

Switching Characteristics table
Updated the Ordering Information table
486690 See ECN VKN Corrected the typo in the 209-Ball FBGA pinout.

Corrected the ball name H9 to VSS from VSSQ .

Page 31 of 31
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1480V33-250BZI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1480V33-250BZI 508048