CY7C1440AV33-167BZCT

CY7C1440AV33-167BZCT Datasheet

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

Part	Datasheet
CY7C1440AV33-167BZCT	CY7C1440AV33-167BZCT (pdf)

Related Parts	Information
CY7C1440AV33-167BZC	CY7C1440AV33-167BZC

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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit 1 M x 36/2 M x 18/512 K x 72 Pipelined Sync SRAM 36-Mbit 1 M x 36/2 M x 18/512 K x 72 Pipelined Sync SRAM • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • V core power supply • V/3.3 V I/O power supply • Fast clock-to-output times ns for 250-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single cycle chip deselect • CY7C1440AV33, CY7C1442AV33 available in Pb-free 100-pin TQFP package, Pb-free and non Pb-free 165-ball FBGA package. CY7C1446AV33 available in Pb-free and non Pb-free 209-ball FBGA package • Also available in Pb-free packages • IEEE JTAG-compatible boundary scan • “ZZ” sleep mode option Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1 M x 36/2 M x 18 and 512 K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3 , burst control inputs ADSC, ADSP, and ADV , write enables BWX and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations see pin descriptions and truth table for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 operates from a V core power supply while all outputs may operate with either a or V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Logic Block Diagram CY7C1440AV33 1 M x 36 A0, A1, A MODE ADV CLK ADSC ADSP BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A[1:0] BURST COUNTER CLR AND Q0 LOGIC DQD ,DQPD BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE DQD ,DQPD BYTE WRITE DRIVER Read Cycle Timing 23 Write Cycle Timing 24 Read/Write Cycle Timing 25 ZZ Mode Timing 26 Ordering Information 27 Ordering Code Definitions 27 Package Diagrams 28 Acronyms 31 Document Conventions 31 Units of Measure 31 Document History Page 32 Sales, Solutions, and Legal Information 34 Worldwide Sales and Design Support 34 Products 34 PSoC Solutions 34 Page 4 of 34 [+] Feedback CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Pin Configurations 250 MHz 200 MHz 167 MHz Unit 100-pin TQFP Pinout ADSP ADSC ADSP ADSC DQPC VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ DQPD CY7C1440AV33 1 M x 36 DQPB 77 76 75 VDDQ VSSQ DQB VDDQ VSSQ 71 70 69 VSSQ VDDQ DQB VSSQ VDDQ DQB VDD NC VSS DQB 61 60 59 VDDQ VSSQ DQA VDDQ VSSQ DQB DQPB 55 54 53 VSSQ VDDQ DQA Ordering Information Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 167 CY7C1440AV33-167AXC 250 CY7C1440AV33-250AXC CY7C1440AV33-250AXI Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free Operating Range Commercial Industrial Ordering Code Definitions CY7C 1440 A V33 - XXX XX X Temperature range X = C or I C = Commercial I = Industrial Package Type XX = AX or BZ AX = 100-pin TQFP Pb-free BZ = 165-ball FPBGA Speed Grade 167 MHz / 250 MHz V33 = V Process Technology 90 nm 1440 = SCD, 1 Mb x 36 Mb CY7C = Cypress SRAMs Page 27 of 34 [+] Feedback Package Diagrams 100-pin TQFP 14 x 20 x mm , 51-85050 CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 51-85050 C Page 28 of 34 [+] Feedback Package Diagrams continued 165-ball FBGA 15 x 17 x mm , 51-85165 CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 51-85165 B Page 29 of 34 [+] Feedback Package Diagrams continued 209-ball FBGA 14 x 22 x mm , 51-85167 CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 51-85167 A Page 30 of 34 [+] Feedback Acronyms Acronym CE CEN CMOS FPBGA I/O JTAG NoBL OE SRAM TCK TMS TDI TDO TQFP WE Description chip enable clock enable complementary metal oxide semiconductor fine-pitch ball grid array input/output Joint Test Action Group No Bus Latency output enable static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Document Conventions Units of Measure Symbol ns V µA mA ms mm MHz pF W °C Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds milli meter Mega Hertz pico Farad Watts degree Celcius Page 31 of 34 [+] Feedback CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Document History Page Document Title CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit 1 M x 36/2 M x 18/512 K x 72 Pipelined Sync SRAM Document Number 38-05383 ECN NO. Issue Date Orig. of Change Description of Change 124437 03/04/03 CJM New data sheet 254910 See ECN by the letter “A” Modified Functional Block diagrams Modified switching waveforms Added Boundary scan information Added Footnote #14 32-Bit Vendor ID Code changed Updated the Ordering Information by Shading and Unshading MPNs as per availability Page 32 of 34 [+] Feedback CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Document Title CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit 1 M x 36/2 M x 18/512 K x 72 Pipelined Sync SRAM Document Number 38-05383 ECN NO. Issue Date Orig. of Change Description of Change 417547 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed IX current value in MODE from & 30 to & 5 respectively and also Changed IX current value in ZZ from & 5 to & 30 respectively on page# 18 Modified test condition in note# 8 from VIH < VDD to VIH VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from A to *B Updated the Ordering Information 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. 2897278 03/22/2010 NJY Removed obsolete part numbers from Ordering Information table and updated package diagrams. 3044512 10/01/2010 NJY Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. 3055212 10/11/2010 NJY Updated Ordering Information. Page 33 of 34 [+] Feedback CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 34 of 34 [+] Feedback

PDF Datasheet Preview

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
36-Mbit 1 M x 36/2 M x 18/512 K x 72 Pipelined Sync SRAM
36-Mbit 1 M x 36/2 M x 18/512 K x 72 Pipelined Sync SRAM
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• V core power supply
• V/3.3 V I/O power supply
• Fast clock-to-output times
ns for 250-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single cycle chip deselect
• CY7C1440AV33, CY7C1442AV33 available in Pb-free 100-pin

TQFP package, Pb-free and non Pb-free 165-ball FBGA package. CY7C1446AV33 available in Pb-free and non Pb-free 209-ball FBGA package
• Also available in Pb-free packages
• IEEE JTAG-compatible boundary scan
• “ZZ” sleep mode option

Functional Description[1]

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1 M x 36/2 M x 18 and 512 K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3 , burst control inputs ADSC, ADSP, and ADV , write enables BWX and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations see pin descriptions and truth table for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.

CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
operates from a V core power supply while all outputs may
operate with either a or V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

Logic Block Diagram CY7C1440AV33 1 M x 36

A0, A1, A

MODE ADV CLK

ADSC ADSP

BWA BWE GW

CE1 CE2 CE3 OE

ADDRESS REGISTER

A[1:0]

BURST COUNTER CLR AND Q0

LOGIC

DQD ,DQPD BYTE

WRITE REGISTER

DQC ,DQPC BYTE

WRITE REGISTER

DQB ,DQPB BYTE

WRITE REGISTER

DQA ,DQPA BYTE

WRITE REGISTER

ENABLE REGISTER

PIPELINED ENABLE

DQD ,DQPD BYTE

WRITE DRIVER
Read Cycle Timing 23 Write Cycle Timing 24 Read/Write Cycle Timing 25 ZZ Mode Timing 26 Ordering Information 27 Ordering Code Definitions 27 Package Diagrams 28 Acronyms 31 Document Conventions 31 Units of Measure 31 Document History Page 32 Sales, Solutions, and Legal Information 34 Worldwide Sales and Design Support 34 Products 34 PSoC Solutions 34

Page 4 of 34 [+] Feedback

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

Selection Guide

Maximum access time Maximum operating current Maximum CMOS standby current

Pin Configurations
250 MHz
200 MHz
167 MHz

Unit
100-pin TQFP Pinout

ADSP

ADSC

ADSP

ADSC

DQPC

VDDQ

VSSQ

VSSQ

VDDQ

VDDQ

VSSQ

VSSQ

VDDQ

DQPD

CY7C1440AV33 1 M x 36

DQPB
77 76 75

VDDQ VSSQ DQB

VDDQ VSSQ
71 70 69

VSSQ VDDQ DQB

VSSQ VDDQ DQB

VDD NC

VSS DQB
61 60 59

VDDQ VSSQ DQA

VDDQ VSSQ DQB

DQPB
55 54 53

VSSQ VDDQ DQA
Ordering Information

Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
167 CY7C1440AV33-167AXC
250 CY7C1440AV33-250AXC

CY7C1440AV33-250AXI

Package Diagram

Part and Package Type
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free

Operating Range

Commercial

Industrial
Ordering Code Definitions CY7C 1440 A V33 - XXX XX X

Temperature range X = C or I C = Commercial I = Industrial Package Type XX = AX or BZ AX = 100-pin TQFP Pb-free BZ = 165-ball FPBGA Speed Grade 167 MHz / 250 MHz V33 = V Process Technology 90 nm 1440 = SCD, 1 Mb x 36 Mb CY7C = Cypress SRAMs

Page 27 of 34 [+] Feedback

Package Diagrams
100-pin TQFP 14 x 20 x mm , 51-85050

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
51-85050 *C

Page 28 of 34 [+] Feedback

Package Diagrams continued
165-ball FBGA 15 x 17 x mm , 51-85165

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
51-85165 *B

Page 29 of 34 [+] Feedback

Package Diagrams continued
209-ball FBGA 14 x 22 x mm , 51-85167

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
51-85167 *A

Page 30 of 34 [+] Feedback

Acronyms

Acronym CE CEN CMOS FPBGA I/O JTAG NoBL OE SRAM TCK TMS TDI TDO TQFP WE

Description chip enable clock enable complementary metal oxide semiconductor fine-pitch ball grid array input/output Joint Test Action Group No Bus Latency output enable static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

Document Conventions

Units of Measure

Symbol ns V µA mA ms mm MHz pF W °C

Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds milli meter Mega Hertz pico Farad Watts degree Celcius

Page 31 of 34 [+] Feedback

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

Document History Page

Document Title CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit 1 M x 36/2 M x 18/512 K x 72 Pipelined Sync SRAM Document Number 38-05383

ECN NO. Issue Date

Orig. of Change

Description of Change
124437 03/04/03

CJM New data sheet
254910 See ECN
by the letter “A”

Modified Functional Block diagrams

Modified switching waveforms

Added Boundary scan information

Added Footnote #14 32-Bit Vendor ID Code changed
Updated the Ordering Information by Shading and Unshading MPNs as per
availability

Page 32 of 34 [+] Feedback

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

Document Title CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit 1 M x 36/2 M x 18/512 K x 72 Pipelined Sync SRAM Document Number 38-05383

ECN NO. Issue Date

Orig. of Change

Description of Change
417547 See ECN RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Changed IX current value in MODE from & 30 to & 5 respectively and also Changed IX current value in ZZ from & 5 to & 30 respectively on page# 18

Modified test condition in note# 8 from VIH < VDD to VIH VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering

Information table

Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
473650 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

AC Switching Characteristics table.
Updated the Ordering Information table.
2897278 03/22/2010 NJY Removed obsolete part numbers from Ordering Information table and
updated package diagrams.
3044512 10/01/2010 NJY Added Ordering Code Definitions.

Added Acronyms and Units of Measure.

Minor edits and updated in new template.
3055212 10/11/2010 NJY Updated Ordering Information.

Page 33 of 34 [+] Feedback

CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 34 of 34
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1440AV33-167BZCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1440AV33-167BZCT 508038