CY7C1424AV18-250BZCT

CY7C1424AV18-250BZCT Datasheet

CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18

Part	Datasheet
CY7C1424AV18-250BZCT	CY7C1424AV18-250BZCT (pdf)

Related Parts	Information
CY7C1424AV18-250BZC	CY7C1424AV18-250BZC

PDF Datasheet Preview
CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage • Available in 165-Ball FBGA package 15 x 17 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations CY7C1422AV18 4M x 8 CY7C1429AV18 4M x 9 CY7C1423AV18 2M x 18 CY7C1424AV18 1M x 36 Functional Description The CY7C1422AV18, CY7C1429AV18, CY7C1423AV18, and CY7C1424AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO DDR-II SIO architecture. The DDR-II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1422AV18, two 9-bit words in the case of CY7C1429AV18, two 18-bit words in the case of CY7C1423AV18, and two 36-bit words in the case of CY7C1424AV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 278 MHz 278 775 815 890 250 MHz 250 700 740 800 200 MHz 200 600 665 167 MHz 167 500 560 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Logic Block Diagram CY7C1422AV18 8 D[7:0] A 20:0 21 Address Register K DOFF CLK Gen. R/W VREF NWS[1:0] Control Logic Write Add. Decode Read Add. Decode Write Write Data Reg Data Reg 2M x 8 Array 2M x 8 Array Read Data Reg. Control Logic Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 300 CY7C1422AV18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429AV18-300BZC CY7C1423AV18-300BZC CY7C1424AV18-300BZC CY7C1422AV18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429AV18-300BZXC CY7C1423AV18-300BZXC CY7C1424AV18-300BZXC CY7C1422AV18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429AV18-300BZI CY7C1423AV18-300BZI CY7C1424AV18-300BZI CY7C1422AV18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429AV18-300BZXI CY7C1423AV18-300BZXI CY7C1424AV18-300BZXI 278 CY7C1422AV18-278BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429AV18-278BZC CY7C1423AV18-278BZC CY7C1424AV18-278BZC CY7C1422AV18-278BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429AV18-278BZXC CY7C1423AV18-278BZXC CY7C1424AV18-278BZXC CY7C1422AV18-278BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429AV18-278BZI Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1422AV18-250BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429AV18-250BZC CY7C1423AV18-250BZC CY7C1424AV18-250BZC CY7C1422AV18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429AV18-250BZXC CY7C1423AV18-250BZXC CY7C1424AV18-250BZXC CY7C1422AV18-250BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429AV18-250BZI CY7C1423AV18-250BZI CY7C1424AV18-250BZI CY7C1422AV18-250BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429AV18-250BZXI CY7C1423AV18-250BZXI CY7C1424AV18-250BZXI 200 CY7C1422AV18-200BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429AV18-200BZC CY7C1423AV18-200BZC CY7C1424AV18-200BZC CY7C1422AV18-200BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429AV18-200BZXC CY7C1423AV18-200BZXC CY7C1424AV18-200BZXC CY7C1422AV18-200BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429AV18-200BZI Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1422AV18-167BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429AV18-167BZC CY7C1423AV18-167BZC CY7C1424AV18-167BZC CY7C1422AV18-167BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429AV18-167BZXC CY7C1423AV18-167BZXC CY7C1424AV18-167BZXC CY7C1422AV18-167BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429AV18-167BZI CY7C1423AV18-167BZI CY7C1424AV18-167BZI CY7C1422AV18-167BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429AV18-167BZXI CY7C1423AV18-167BZXI CY7C1424AV18-167BZXI Page 28 of 31 [+] Feedback Package Diagram CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Figure 165-ball FBGA 15 x 17 x mm , 51-85195 ! " # % & ' * + , 0 2 ! " # % & ' * + , 0 2 51-85195-A Page 29 of 31 [+] Feedback CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Document History Page Document Title 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number 38-05617 ECN NO. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE A 326519 See ECN SYT Removed CY7C1429AV18 from the title Included 300 MHz Speed grade Replaced TBDs with their respective values for IDD and ISB1 Added Industrial temperature Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 17.2°C/W and ΘJC = 3.2°C/W Replaced TBDs in the Capacitance Table to their respective values for the 165 FBGA Package Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS TRI-STATE on Page 17 Added lead-free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per availability B 413953 See ECN NXR Converted from preliminary to final Added CY7C1429AV18 part number to title Added 278-MHz speed Bin Changed C, C Description in Feature Section and Pin Description Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added Power-up sequence and Wave form on page# 18 Added Footnote# 13, 14, 15 on page# 18 Replaced Three-state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 19 Modified the IDD and ISB values Modified test condition in Footnote #17 on page# 19 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table C 468029 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from to +85°C to +125°C Added additional notes in the AC parameter section Modified AC Switching Waveform Updated the Typo in the AC Switching Characteristics Table Updated the Ordering Information Table Page 30 of 31 [+] Feedback CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Document History Page Document Title 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number 38-05617 *D 2511746 See ECN VKN/AESA Updated Logic Block diagram Updated IDD/ISB specs Added footnote# 19 related to IDD Updated Power-up sequence waveform and it’s description Changed DLL minimum operating frequency from 80MHz to 120MHz Changed tCYC max spec to 8.4ns for all speed bins Modified footnotes 21 and 28 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 31 of 31 DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
• 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36
• 300 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double Data Rate DDR interfaces
data transferred at 600 MHz at 300 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high-speed
systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage
• Available in 165-Ball FBGA package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

CY7C1422AV18 4M x 8 CY7C1429AV18 4M x 9 CY7C1423AV18 2M x 18 CY7C1424AV18 1M x 36

Functional Description

The CY7C1422AV18, CY7C1429AV18, CY7C1423AV18, and CY7C1424AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO DDR-II SIO architecture. The DDR-II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1422AV18, two 9-bit words in the case of CY7C1429AV18, two 18-bit words in the case of CY7C1423AV18, and two 36-bit words in the case of CY7C1424AV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
300 MHz
278 MHz 278 775 815 890
250 MHz 250 700 740 800
200 MHz 200 600 665
167 MHz 167 500 560

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18

Logic Block Diagram CY7C1422AV18
8 D[7:0]

A 20:0 21

Address Register

K DOFF

CLK Gen.

R/W VREF

NWS[1:0]

Control Logic

Write Add. Decode Read Add. Decode

Write

Write

Data Reg Data Reg
2M x 8 Array 2M x 8 Array

Read Data Reg.

Control

Logic
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
300 CY7C1422AV18-300BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1429AV18-300BZC

CY7C1423AV18-300BZC

CY7C1424AV18-300BZC

CY7C1422AV18-300BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1429AV18-300BZXC

CY7C1423AV18-300BZXC

CY7C1424AV18-300BZXC

CY7C1422AV18-300BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1429AV18-300BZI

CY7C1423AV18-300BZI

CY7C1424AV18-300BZI

CY7C1422AV18-300BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1429AV18-300BZXI

CY7C1423AV18-300BZXI

CY7C1424AV18-300BZXI
278 CY7C1422AV18-278BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1429AV18-278BZC

CY7C1423AV18-278BZC

CY7C1424AV18-278BZC

CY7C1422AV18-278BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1429AV18-278BZXC

CY7C1423AV18-278BZXC

CY7C1424AV18-278BZXC

CY7C1422AV18-278BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1429AV18-278BZI
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1422AV18-250BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1429AV18-250BZC

CY7C1423AV18-250BZC

CY7C1424AV18-250BZC

CY7C1422AV18-250BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1429AV18-250BZXC

CY7C1423AV18-250BZXC

CY7C1424AV18-250BZXC

CY7C1422AV18-250BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1429AV18-250BZI

CY7C1423AV18-250BZI

CY7C1424AV18-250BZI

CY7C1422AV18-250BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1429AV18-250BZXI

CY7C1423AV18-250BZXI

CY7C1424AV18-250BZXI
200 CY7C1422AV18-200BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1429AV18-200BZC

CY7C1423AV18-200BZC

CY7C1424AV18-200BZC

CY7C1422AV18-200BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1429AV18-200BZXC

CY7C1423AV18-200BZXC

CY7C1424AV18-200BZXC

CY7C1422AV18-200BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1429AV18-200BZI
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1422AV18-167BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1429AV18-167BZC

CY7C1423AV18-167BZC

CY7C1424AV18-167BZC

CY7C1422AV18-167BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1429AV18-167BZXC

CY7C1423AV18-167BZXC

CY7C1424AV18-167BZXC

CY7C1422AV18-167BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1429AV18-167BZI

CY7C1423AV18-167BZI

CY7C1424AV18-167BZI

CY7C1422AV18-167BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1429AV18-167BZXI

CY7C1423AV18-167BZXI

CY7C1424AV18-167BZXI

Page 28 of 31 [+] Feedback

Package Diagram

CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18

Figure 165-ball FBGA 15 x 17 x mm , 51-85195
! " # % & ' * + , 0 2
! " # % & ' * + , 0 2
51-85195-*A

Page 29 of 31 [+] Feedback

CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18

Document History Page

Document Title 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number 38-05617

ECN NO.

ISSUE DATE

ORIG. OF CHANGE

DESCRIPTION OF CHANGE
*A 326519 See ECN SYT Removed CY7C1429AV18 from the title Included 300 MHz Speed grade Replaced TBDs with their respective values for IDD and ISB1 Added Industrial temperature Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 17.2°C/W and ΘJC = 3.2°C/W Replaced TBDs in the Capacitance Table to their respective values for the 165 FBGA Package Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS TRI-STATE on Page 17 Added lead-free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per availability
*B 413953 See ECN NXR Converted from preliminary to final Added CY7C1429AV18 part number to title Added 278-MHz speed Bin Changed C, C Description in Feature Section and Pin Description Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added Power-up sequence and Wave form on page# 18 Added Footnote# 13, 14, 15 on page# 18 Replaced Three-state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 19 Modified the IDD and ISB values Modified test condition in Footnote #17 on page# 19 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table
*C 468029 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from to +85°C to +125°C Added additional notes in the AC parameter section Modified AC Switching Waveform Updated the Typo in the AC Switching Characteristics Table Updated the Ordering Information Table

Page 30 of 31 [+] Feedback

CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18

Document History Page

Document Title 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number 38-05617
*D 2511746 See ECN VKN/AESA Updated Logic Block diagram Updated IDD/ISB specs Added footnote# 19 related to IDD Updated Power-up sequence waveform and it’s description Changed DLL minimum operating frequency from 80MHz to 120MHz Changed tCYC max spec to 8.4ns for all speed bins Modified footnotes 21 and 28

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

PSoC Solutions

General
psoc.cypress.com/solutions

Low Power/Low Voltage
psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
psoc.cypress.com/usb

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 31 of 31

DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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Datasheet ID: CY7C1424AV18-250BZCT 508026