CY7C1418AV18-267BZXC

CY7C1418AV18-267BZXC Datasheet

CY7C1418AV18 CY7C1420AV18

Part	Datasheet
CY7C1418AV18-267BZXC	CY7C1418AV18-267BZXC (pdf)

Related Parts	Information
CY7C1420AV18-200BZC	CY7C1420AV18-200BZC
CY7C1420AV18-250BZC	CY7C1420AV18-250BZC
CY7C1418AV18-267BZC	CY7C1418AV18-267BZC
CY7C1420AV18-167BZXC	CY7C1420AV18-167BZXC
CY7C1420AV18-200BZCT	CY7C1420AV18-200BZCT
CY7C1418AV18-250BZC	CY7C1418AV18-250BZC

PDF Datasheet Preview
CY7C1418AV18 CY7C1420AV18 36 Mbit DDR II SRAM Two Word Burst Architecture • 36 Mbit density 2M x 18, 1M x 36 • 300 MHz clock for high bandwidth • Two word burst for reducing address bus frequency • Double Data Rate DDR interfaces  data transferred at 600MHz at 300 MHz for DDR II • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high speed systems • Synchronous internally self timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage • Available in 165-Ball FBGA package 15 x 17 x mm • Offered in both in Pb-free and non Pb-free packages • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations CY7C1418AV18 2M x 18 CY7C1420AV18 1M x 36 Functional Description The CY7C1418AV18, and CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1 bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. On CY7C1418AV18 and CY7C1420AV18, the burst counter takes in the least significant bit of the external address and bursts two 18 bit words in the case of CY7C1418AV18 and two 36 bit words in the case of CY7C1420AV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self timed write circuitry. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 278 MHz 278 835 910 250 MHz 250 760 825 200 MHz 200 620 675 167 MHz 167 525 570 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1418AV18 CY7C1420AV18 Logic Block Diagram CY7C1418AV18 Burst Logic A 20:0 21 20 A 20:1 Address Register K DOFF CLK Gen. VREF R/W BWS[1:0] Control Logic Write Reg Write Reg 1M x 18 Array 1M x 18 Array Read Data Reg. 36 18 Write Add. Decode Read Add. Decode Output Logic Control Reg. Reg. 18 Reg. Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 267 CY7C1418AV18-267BZC CY7C1418AV18-267BZXC 250 CY7C1418AV18-250BZC CY7C1420AV18-250BZC 200 CY7C1420AV18-200BZC 167 CY7C1420AV18-167BZXC Package Diagram Package Type Operating Range 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free Commercial Ordering Code Definition CY 7 C 14XX A V18 - XXX BZ X, C, I Package Type  BZ = FBGA, X = Pb-free, C = Commercial Maximum operating frequency Voltage V 90 nm 36-Mbit DDR II SRAM 2-word burst architecture Technology CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Page 24 of 27 [+] Feedback Package Diagram Figure 165-ball FBGA 15 x 17 x mm CY7C1418AV18 CY7C1420AV18 51-85195 B Page 25 of 27 [+] Feedback CY7C1418AV18 CY7C1420AV18 Document History Page Document Title CY7C1418AV18, CY7C1420AV18, 36 Mbit DDR II SRAM Two Word Burst Architecture Document Number 38-05616 Oirg. Of Change Submission Date Description Of Change 247331 08/26/04 New Datasheet 326519 04/14/05 Removed CY7C1420AV18 from the title Included 300 MHz Speed grade Replaced TBDs with their respective values for IDD and ISB1 Added Industrial temperature grade Replaced the TBDs on the Thermal Characteristics Table to = 17.2C/W and = 3.2C/W Replaced TBDs in the Capacitance Table to their respective values for the 165 FBGA Package Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS TRI-STATE on Page 18 Added lead-free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per availability 413953 12/22/05 Converted from preliminary to final Added CY7C1427AV18 part number to title Added 278 MHz speed Bin Changed C, C Description in Feature Section and Pin Description Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added Power Up sequence and Wave form on page# 19 Added Footnotes# 13, 14, 15 on page# 19 Replaced Three-state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 20 Modified the IDD and ISB values Modified test condition in Footnote #17 on page# 20 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table. Updated Ordering Information Table 468029 07/10/06 Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from C to +85 C to C to +125 C Added additional notes in the AC parameter section Modified AC Switching Waveform Corrected the typo In the AC Switching Characteristics Table Updated the Ordering Information Table 505682 12/19/06 Corrected typo in the Functional Description section for burst counter logic E 2511757 VKN/AESA 06/19/08 Updated Logic Block diagram Updated IDD/ISB specs Added footnote # 19 related to IDD Updated Power Up sequence waveform and its description Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed tCYC max spec to ns for all speed bins Modified footnotes 21 and 28 Page 26 of 27 [+] Feedback CY7C1418AV18 CY7C1420AV18 Document History Page Document Title CY7C1418AV18, CY7C1420AV18, 36 Mbit DDR II SRAM Two Word Burst Architecture Document Number 38-05616 Oirg. of Change Submission Date Description of Change 2648034 PYRS 01/29/09 Moved to external web G 2755901 08/25/09 Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Updated Package Diagram. H 2897120 03/22/2010 Removed inactive parts from Ordering Information table. 3068494 10/21/2010 HMLA Removed inactive part - CY7C1420AV18-278BZC, and active parts CY7C1418AV18-267BZC, CY7C1418AV18-267BZXC in Ordering Information table. Added Ordering Code Definition. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 27 of 27 DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1418AV18 CY7C1420AV18
36 Mbit DDR II SRAM Two Word Burst Architecture
• 36 Mbit density 2M x 18, 1M x 36
• 300 MHz clock for high bandwidth
• Two word burst for reducing address bus frequency
• Double Data Rate DDR interfaces 
data transferred at 600MHz at 300 MHz for DDR II
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high speed
systems
• Synchronous internally self timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage
• Available in 165-Ball FBGA package 15 x 17 x mm
• Offered in both in Pb-free and non Pb-free packages
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

CY7C1418AV18 2M x 18 CY7C1420AV18 1M x 36

Functional Description

The CY7C1418AV18, and CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1 bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. On CY7C1418AV18 and CY7C1420AV18, the burst counter takes in the least significant bit of the external address and bursts two 18 bit words in the case of CY7C1418AV18 and two 36 bit words in the case of CY7C1420AV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self timed write circuitry.

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
300 MHz
278 MHz 278 835 910
250 MHz 250 760 825
200 MHz 200 620 675
167 MHz 167 525 570

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1418AV18 CY7C1420AV18

Logic Block Diagram CY7C1418AV18

Burst Logic

A 20:0
21 20 A 20:1

Address Register

K DOFF

CLK Gen.

VREF R/W BWS[1:0]

Control Logic

Write Reg

Write Reg
1M x 18 Array 1M x 18 Array

Read Data Reg. 36 18

Write Add. Decode Read Add. Decode

Output Logic

Control

Reg.

Reg. 18

Reg.
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
267 CY7C1418AV18-267BZC

CY7C1418AV18-267BZXC
250 CY7C1418AV18-250BZC

CY7C1420AV18-250BZC
200 CY7C1420AV18-200BZC
167 CY7C1420AV18-167BZXC

Package Diagram

Package Type

Operating Range
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial
165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free Commercial
Ordering Code Definition

CY 7 C
14XX

A V18 - XXX BZ X, C, I

Package Type  BZ = FBGA, X = Pb-free, C = Commercial

Maximum operating frequency

Voltage V
90 nm 36-Mbit DDR II SRAM 2-word burst architecture

Technology CMOS Marketing Code 7 = SRAM

Company ID CY = Cypress

Page 24 of 27 [+] Feedback

Package Diagram

Figure 165-ball FBGA 15 x 17 x mm

CY7C1418AV18 CY7C1420AV18
51-85195 *B

Page 25 of 27 [+] Feedback

CY7C1418AV18 CY7C1420AV18

Document History Page

Document Title CY7C1418AV18, CY7C1420AV18, 36 Mbit DDR II SRAM Two Word Burst Architecture Document Number 38-05616

Oirg. Of Change

Submission Date

Description Of Change
247331
08/26/04 New Datasheet
326519
04/14/05
Removed CY7C1420AV18 from the title Included 300 MHz Speed grade Replaced TBDs with their respective values for IDD and ISB1 Added Industrial temperature grade Replaced the TBDs on the Thermal Characteristics Table to = 17.2C/W and = 3.2C/W Replaced TBDs in the Capacitance Table to their respective values for the 165 FBGA Package Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS TRI-STATE on Page 18 Added lead-free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per availability
413953
12/22/05
Converted from preliminary to final Added CY7C1427AV18 part number to title Added 278 MHz speed Bin Changed C, C Description in Feature Section and Pin Description Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added Power Up sequence and Wave form on page# 19 Added Footnotes# 13, 14, 15 on page# 19 Replaced Three-state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 20 Modified the IDD and ISB values Modified test condition in Footnote #17 on page# 20 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table. Updated Ordering Information Table
468029
07/10/06
Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from C to +85 C to C to +125 C Added additional notes in the AC parameter section Modified AC Switching Waveform Corrected the typo In the AC Switching Characteristics Table Updated the Ordering Information Table
505682
12/19/06 Corrected typo in the Functional Description section for burst counter logic
*E 2511757 VKN/AESA
06/19/08

Updated Logic Block diagram Updated IDD/ISB specs Added footnote # 19 related to IDD Updated Power Up sequence waveform and its description Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed tCYC max spec to ns for all speed bins Modified footnotes 21 and 28

Page 26 of 27 [+] Feedback

CY7C1418AV18 CY7C1420AV18

Document History Page

Document Title CY7C1418AV18, CY7C1420AV18, 36 Mbit DDR II SRAM Two Word Burst Architecture Document Number 38-05616

Oirg. of Change

Submission Date

Description of Change
2648034

PYRS
01/29/09 Moved to external web
*G 2755901
08/25/09
Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Updated Package Diagram.
*H 2897120 03/22/2010
Removed inactive parts from Ordering Information table.
3068494 10/21/2010

HMLA
Removed inactive part - CY7C1420AV18-278BZC, and active parts CY7C1418AV18-267BZC, CY7C1418AV18-267BZXC in Ordering Information table. Added Ordering Code Definition.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 27 of 27

DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1418AV18-267BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1418AV18-267BZXC 508025