CY7C1414BV18-200BZXI

CY7C1414BV18-200BZXI Datasheet

CY7C1412BV18 CY7C1414BV18

Part	Datasheet
CY7C1414BV18-200BZXI	CY7C1414BV18-200BZXI (pdf)

Related Parts	Information
CY7C1414BV18-200BZI	CY7C1414BV18-200BZI
CY7C1412BV18-167BZXI	CY7C1412BV18-167BZXI
CY7C1412BV18-200BZXC	CY7C1412BV18-200BZXC
CY7C1414BV18-250BZXI	CY7C1414BV18-250BZXI
CY7C1412BV18-250BZXC	CY7C1412BV18-250BZXC

PDF Datasheet Preview
CY7C1412BV18 CY7C1414BV18 36-Mbit II SRAM 2-Word Burst Architecture • Separate independent Read and Write Data Ports Supports concurrent transactions • 250 MHz clock for high bandwidth • 2-word burst on all accesses • Double Data Rate DDR interfaces on both read and write ports data transferred at 500 MHz at 250 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both read and write ports • Separate port selects for depth expansion • Synchronous internally self-timed writes • II operates with cycle read latency when Delay Lock Loop DLL is enabled • Operates as a QDR I device with 1 cycle read latency in DLL off mode • Available in x 18, and x 36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD • Available in 165-Ball FBGA package 15 x 17 x mm • Offered in both Pb-free and non Pb-free packages • Variable drive HSTL output buffers • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Selection Guide Maximum Operating Frequency Maximum Operating Current 250 MHz 250 850 1000 Configurations CY7C1412BV18 2M x 18 CY7C1414BV18 1M x 36 Functional Description The CY7C1412BV18, and CY7C1414BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 18-bit words CY7C1412BV18 , or 36-bit words CY7C1414BV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus ‘turnarounds’. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. 200 MHz 200 725 850 167 MHz 167 650 740 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1412BV18 CY7C1412BV18 CY7C1414BV18 D[17:0] A 19:0 20 Address Register K DOFF VREF WPS BWS[1:0] CLK Gen. Control Logic Write Add. Decode Read Add. Decode Write Reg Write Reg Address Register A 19:0 1M x 18 Array 1M x 18 Array Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1412BV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free Commercial CY7C1414BV18-250BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free Industrial 200 CY7C1412BV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free Commercial CY7C1414BV18-200BZI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1414BV18-200BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free 167 CY7C1412BV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free Industrial Ordering Code Definitions CY7C 14XX B V18 - XXX X Temperature Range X = C or I C = Commercial I = Industrial Package Type XXX = BZX or BZ BZX = 165-ball FPBGA Pb-free BZ = 165-ball FPBGA Speed XXX = 250 MHz / 200 MHz / 167 MHz V18 = V Process Technology B = 90 nm Part Identifier CY7C = Cypress SRAMs Page 22 of 25 [+] Feedback Package Diagram CY7C1412BV18 CY7C1414BV18 Figure 165-ball FBGA 15 x 17 x mm , 51-85195 51-85195 B Page 23 of 25 [+] Feedback CY7C1412BV18 CY7C1414BV18 Document History Page Document Title CY7C1412BV18/CY7C1414BV18, 36-Mbit II SRAM 2-Word Burst Architecture Document Number 001-07036 Submission Date Orig. of Change Description of Change * 433267 See ECN NXR New Data Sheet A 462004 See ECN B 503690 See ECN NXR VKN Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Minor change Moved data sheet to web C 1523289 See ECN VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated IDD/ISB specs, Changed DLL minimum operating frequency from 80MHz to 120MHz, Changed tCYC max spec to 8.4ns for all speed bins, Modified footnotes 20 and 28 D 2478647 See ECN VKN/AESA Changed Ambient Temperature with Power Applied from C to +85 C” to C to +125 C” in the “Maximum Ratings “on page 20, Updated Power-up sequence waveform and it’s description, Updated IDD/ISB specs, Added footnote #19 related to IDD, Changed JTAG ID [31:29] from 001 to E 2755831 08/25/2009 VKN/AESA Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. F 3101004 12/03/2010 NJY Updated Ordering Information and added Ordering Code Definitions. Updated Package Diagram. Page 24 of 25 [+] Feedback CY7C1412BV18 CY7C1414BV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 25 of 25 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1412BV18 CY7C1414BV18
36-Mbit II SRAM 2-Word Burst Architecture
• Separate independent Read and Write Data Ports Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 2-word burst on all accesses
• Double Data Rate DDR interfaces on both read and write ports
data transferred at 500 MHz at 250 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high-speed
systems
• Single multiplexed address input bus latches address inputs
for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• II operates with cycle read latency when Delay Lock

Loop DLL is enabled
• Operates as a QDR I device with 1 cycle read latency in DLL
off mode
• Available in x 18, and x 36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free packages
• Variable drive HSTL output buffers
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Selection Guide

Maximum Operating Frequency

Maximum Operating Current
250 MHz 250 850 1000

Configurations

CY7C1412BV18 2M x 18 CY7C1414BV18 1M x 36

Functional Description

The CY7C1412BV18, and CY7C1414BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 18-bit words CY7C1412BV18 , or 36-bit words CY7C1414BV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus ‘turnarounds’.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
200 MHz 200 725 850
167 MHz 167 650 740

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1412BV18

CY7C1412BV18 CY7C1414BV18

D[17:0]

A 19:0 20

Address Register

K DOFF

VREF WPS BWS[1:0]

CLK Gen.

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg

Address Register

A 19:0
1M x 18 Array 1M x 18 Array
Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1412BV18-250BZXC
51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free Commercial

CY7C1414BV18-250BZXI
51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free Industrial
200 CY7C1412BV18-200BZXC
51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free Commercial

CY7C1414BV18-200BZI
51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1414BV18-200BZXI
51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free
167 CY7C1412BV18-167BZXI
51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-free Industrial
Ordering Code Definitions CY7C 14XX B V18 - XXX X

Temperature Range X = C or I C = Commercial I = Industrial Package Type XXX = BZX or BZ BZX = 165-ball FPBGA Pb-free BZ = 165-ball FPBGA Speed XXX = 250 MHz / 200 MHz / 167 MHz V18 = V Process Technology B = 90 nm Part Identifier CY7C = Cypress SRAMs

Page 22 of 25 [+] Feedback

Package Diagram

CY7C1412BV18 CY7C1414BV18

Figure 165-ball FBGA 15 x 17 x mm , 51-85195
51-85195 *B

Page 23 of 25 [+] Feedback

CY7C1412BV18 CY7C1414BV18

Document History Page

Document Title CY7C1412BV18/CY7C1414BV18, 36-Mbit II SRAM 2-Word Burst Architecture Document Number 001-07036

Submission Date

Orig. of Change

Description of Change
** 433267

See ECN

NXR New Data Sheet
*A 462004

See ECN
*B 503690

See ECN

NXR VKN

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Minor change Moved data sheet to web
*C 1523289

See ECN

VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated IDD/ISB specs, Changed DLL minimum operating frequency from 80MHz to 120MHz, Changed tCYC max spec to 8.4ns for all speed bins, Modified footnotes 20 and 28
*D 2478647

See ECN

VKN/AESA Changed Ambient Temperature with Power Applied from C to +85 C” to C to +125 C” in the “Maximum Ratings “on page 20, Updated Power-up
sequence waveform and it’s description, Updated IDD/ISB specs, Added footnote #19 related to IDD, Changed JTAG ID [31:29] from 001 to
*E 2755831 08/25/2009 VKN/AESA Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information.
*F 3101004 12/03/2010
NJY Updated Ordering Information and added Ordering Code Definitions. Updated Package Diagram.

Page 24 of 25 [+] Feedback

CY7C1412BV18 CY7C1414BV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 25 of 25

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1414BV18-200BZXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1414BV18-200BZXI 508022