CY7C1425JV18-250BZI

CY7C1425JV18-250BZI Datasheet

CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18

Part	Datasheet
CY7C1425JV18-250BZI	CY7C1425JV18-250BZI (pdf)

Related Parts	Information
CY7C1414JV18-267BZC	CY7C1414JV18-267BZC
CY7C1425JV18-250BZC	CY7C1425JV18-250BZC
CY7C1425JV18-267BZI	CY7C1425JV18-267BZI
CY7C1414JV18-250BZXC	CY7C1414JV18-250BZXC
CY7C1425JV18-250BZXC	CY7C1425JV18-250BZXC

PDF Datasheet Preview
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit QDR -II SRAM 2-Word Burst Architecture • Separate Independent Read and Write Data Ports Supports concurrent transactions • 267 MHz Clock for High Bandwidth • 2-word Burst on all Accesses • Double Data Rate DDR Interfaces on both Read and Write Ports data transferred at 534 MHz at 267 MHz • Two Input Clocks K and K for Precise DDR Timing SRAM uses rising edges only • Two Input Clocks for Output Data C and C to Minimize Clock Skew and Flight Time Mismatches • Echo Clocks CQ and CQ Simplify Data Capture in High Speed Systems • Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports • Separate Port Selects for Depth Expansion • Synchronous Internally Self-timed Writes • QDR -II operates with Cycle Read latency when Delay Lock Loop DLL is enabled • Operates like a QDR-I device with 1 Cycle Read Latency in DLL Off Mode • Available in x8, x9, x18, and x36 configurations • Full Data Coherency, providing most Current Data • Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD • Available in 165-Ball FBGA Package 15 x 17 x mm • Offered in both Pb-free and non Pb-free packages • Variable Drive HSTL Output Buffers • JTAG Compatible Test Access Port • Delay Lock Loop DLL for Accurate Data Placement Configurations CY7C1410JV18 4M x 8 CY7C1425JV18 4M x 9 CY7C1412JV18 2M x 18 CY7C1414JV18 1M x 36 Functional Description The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports the read port and the write port, to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 8-bit words CY7C1410JV18 , 9-bit words CY7C1425JV18 , 18-bit words CY7C1412JV18 , or 36-bit words CY7C1414JV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus ‘turnarounds’. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 267 MHz 1330 1330 1370 1460 250 MHz 250 1200 1230 1290 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 267 CY7C1410JV18-267BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1425JV18-267BZC CY7C1412JV18-267BZC CY7C1414JV18-267BZC CY7C1410JV18-267BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1425JV18-267BZXC CY7C1412JV18-267BZXC CY7C1414JV18-267BZXC CY7C1410JV18-267BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1425JV18-267BZI CY7C1412JV18-267BZI CY7C1414JV18-267BZI CY7C1410JV18-267BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1425JV18-267BZXI CY7C1412JV18-267BZXI CY7C1414JV18-267BZXI 250 CY7C1410JV18-250BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1425JV18-250BZC CY7C1412JV18-250BZC CY7C1414JV18-250BZC CY7C1410JV18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1425JV18-250BZXC CY7C1412JV18-250BZXC CY7C1414JV18-250BZXC CY7C1410JV18-250BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1425JV18-250BZI

PDF Datasheet Preview

CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18
36-Mbit QDR -II SRAM 2-Word Burst Architecture
• Separate Independent Read and Write Data Ports Supports concurrent transactions
• 267 MHz Clock for High Bandwidth
• 2-word Burst on all Accesses
• Double Data Rate DDR Interfaces on both Read and Write Ports data transferred at 534 MHz at 267 MHz
• Two Input Clocks K and K for Precise DDR Timing SRAM uses rising edges only
• Two Input Clocks for Output Data C and C to Minimize Clock Skew and Flight Time Mismatches
• Echo Clocks CQ and CQ Simplify Data Capture in High Speed Systems
• Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports
• Separate Port Selects for Depth Expansion
• Synchronous Internally Self-timed Writes
• QDR -II operates with Cycle Read latency when Delay Lock Loop DLL is enabled
• Operates like a QDR-I device with 1 Cycle Read Latency in DLL Off Mode
• Available in x8, x9, x18, and x36 configurations
• Full Data Coherency, providing most Current Data
• Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA Package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free packages
• Variable Drive HSTL Output Buffers
• JTAG Compatible Test Access Port
• Delay Lock Loop DLL for Accurate Data Placement

Configurations

CY7C1410JV18 4M x 8

CY7C1425JV18 4M x 9

CY7C1412JV18 2M x 18

CY7C1414JV18 1M x 36

Functional Description

The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports the read port and the write port, to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 8-bit words CY7C1410JV18 , 9-bit words CY7C1425JV18 , 18-bit words CY7C1412JV18 , or 36-bit words CY7C1414JV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus ‘turnarounds’.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
267 MHz
1330
1330
1370
1460
250 MHz 250 1200 1230 1290

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
267 CY7C1410JV18-267BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1425JV18-267BZC

CY7C1412JV18-267BZC

CY7C1414JV18-267BZC

CY7C1410JV18-267BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1425JV18-267BZXC

CY7C1412JV18-267BZXC

CY7C1414JV18-267BZXC

CY7C1410JV18-267BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1425JV18-267BZI

CY7C1412JV18-267BZI

CY7C1414JV18-267BZI

CY7C1410JV18-267BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1425JV18-267BZXI

CY7C1412JV18-267BZXI

CY7C1414JV18-267BZXI
250 CY7C1410JV18-250BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1425JV18-250BZC

CY7C1412JV18-250BZC

CY7C1414JV18-250BZC

CY7C1410JV18-250BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1425JV18-250BZXC

CY7C1412JV18-250BZXC

CY7C1414JV18-250BZXC

CY7C1410JV18-250BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1425JV18-250BZI

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Datasheet ID: CY7C1425JV18-250BZI 508018