CY7C1392CV18-200BZC

CY7C1392CV18-200BZC Datasheet

CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18

Part	Datasheet
CY7C1392CV18-200BZC	CY7C1392CV18-200BZC (pdf)

Related Parts	Information
CY7C1392CV18-250BZC	CY7C1392CV18-250BZC

PDF Datasheet Preview
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Synchronous internally self-timed writes • DDR-II operates with cycle read latency when the DLL is enabled • Operates similar to a DDR-I device with 1 cycle read latency in DLL off mode • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage • Available in 165-Ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO DDR-II SIO architecture. The DDR-II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1392CV18, two 9-bit words in the case of CY7C1992CV18, two 18-bit words in the case of CY7C1393CV18, and two 36-bit words in the case of CY7C1394CV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. CY7C1392CV18 2M x 8 CY7C1992CV18 2M x 9 CY7C1393CV18 1M x 18 CY7C1394CV18 512K x 36 Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 278 MHz 278 770 775 800 850 250 MHz 250 700 725 770 200 MHz 200 575 600 630 167 MHz 167 485 490 500 540 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Logic Block Diagram CY7C1392CV18 8 D[7:0] A 19:0 20 Address Register K DOFF CLK Gen. R/W VREF NWS[1:0] Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 300 CY7C1392CV18-300BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1992CV18-300BZC CY7C1393CV18-300BZC CY7C1394CV18-300BZC CY7C1392CV18-300BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1992CV18-300BZXC CY7C1393CV18-300BZXC CY7C1394CV18-300BZXC CY7C1392CV18-300BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1992CV18-300BZI CY7C1393CV18-300BZI CY7C1394CV18-300BZI CY7C1392CV18-300BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1992CV18-300BZXI CY7C1393CV18-300BZXI CY7C1394CV18-300BZXI 278 CY7C1392CV18-278BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1992CV18-278BZC CY7C1393CV18-278BZC CY7C1394CV18-278BZC CY7C1392CV18-278BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1992CV18-278BZXC CY7C1393CV18-278BZXC CY7C1394CV18-278BZXC CY7C1392CV18-278BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1992CV18-278BZI Ordering Information continued Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1392CV18-250BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1992CV18-250BZC CY7C1393CV18-250BZC CY7C1394CV18-250BZC CY7C1392CV18-250BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1992CV18-250BZXC CY7C1393CV18-250BZXC CY7C1394CV18-250BZXC CY7C1392CV18-250BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1992CV18-250BZI CY7C1393CV18-250BZI CY7C1394CV18-250BZI CY7C1392CV18-250BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1992CV18-250BZXI CY7C1393CV18-250BZXI CY7C1394CV18-250BZXI 200 CY7C1392CV18-200BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1992CV18-200BZC CY7C1393CV18-200BZC CY7C1394CV18-200BZC CY7C1392CV18-200BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1992CV18-200BZXC CY7C1393CV18-200BZXC CY7C1394CV18-200BZXC CY7C1392CV18-200BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1992CV18-200BZI Ordering Information continued Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1392CV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1992CV18-167BZC CY7C1393CV18-167BZC CY7C1394CV18-167BZC CY7C1392CV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1992CV18-167BZXC CY7C1393CV18-167BZXC CY7C1394CV18-167BZXC CY7C1392CV18-167BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1992CV18-167BZI CY7C1393CV18-167BZI CY7C1394CV18-167BZI CY7C1392CV18-167BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1992CV18-167BZXI CY7C1393CV18-167BZXI CY7C1394CV18-167BZXI Page 28 of 30 [+] Feedback CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B - 01.0665X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X

PDF Datasheet Preview

CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

Functional Description
• 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36
• 300 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz
• Two input clocks K and K for precise DDR timing SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• DDR-II operates with cycle read latency when the DLL is enabled
• Operates similar to a DDR-I device with 1 cycle read latency in DLL off mode
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage
• Available in 165-Ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO DDR-II SIO architecture. The DDR-II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1392CV18, two 9-bit words in the case of CY7C1992CV18, two 18-bit words in the case of CY7C1393CV18, and two 36-bit words in the case of CY7C1394CV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

CY7C1392CV18 2M x 8 CY7C1992CV18 2M x 9 CY7C1393CV18 1M x 18 CY7C1394CV18 512K x 36

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
300 MHz
278 MHz 278 770 775 800 850
250 MHz 250 700 725 770
200 MHz 200 575 600 630
167 MHz 167 485 490 500 540

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18

Logic Block Diagram CY7C1392CV18
8 D[7:0]

A 19:0 20

Address Register

K DOFF

CLK Gen.

R/W VREF

NWS[1:0]
Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
300 CY7C1392CV18-300BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1992CV18-300BZC

CY7C1393CV18-300BZC

CY7C1394CV18-300BZC

CY7C1392CV18-300BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1992CV18-300BZXC

CY7C1393CV18-300BZXC

CY7C1394CV18-300BZXC

CY7C1392CV18-300BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1992CV18-300BZI

CY7C1393CV18-300BZI

CY7C1394CV18-300BZI

CY7C1392CV18-300BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1992CV18-300BZXI

CY7C1393CV18-300BZXI

CY7C1394CV18-300BZXI
278 CY7C1392CV18-278BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1992CV18-278BZC

CY7C1393CV18-278BZC

CY7C1394CV18-278BZC

CY7C1392CV18-278BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1992CV18-278BZXC

CY7C1393CV18-278BZXC

CY7C1394CV18-278BZXC

CY7C1392CV18-278BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1992CV18-278BZI
Ordering Information continued

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1392CV18-250BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1992CV18-250BZC

CY7C1393CV18-250BZC

CY7C1394CV18-250BZC

CY7C1392CV18-250BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1992CV18-250BZXC

CY7C1393CV18-250BZXC

CY7C1394CV18-250BZXC

CY7C1392CV18-250BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1992CV18-250BZI

CY7C1393CV18-250BZI

CY7C1394CV18-250BZI

CY7C1392CV18-250BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1992CV18-250BZXI

CY7C1393CV18-250BZXI

CY7C1394CV18-250BZXI
200 CY7C1392CV18-200BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1992CV18-200BZC

CY7C1393CV18-200BZC

CY7C1394CV18-200BZC

CY7C1392CV18-200BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1992CV18-200BZXC

CY7C1393CV18-200BZXC

CY7C1394CV18-200BZXC

CY7C1392CV18-200BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1992CV18-200BZI
Ordering Information continued

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1392CV18-167BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1992CV18-167BZC

CY7C1393CV18-167BZC

CY7C1394CV18-167BZC

CY7C1392CV18-167BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1992CV18-167BZXC

CY7C1393CV18-167BZXC

CY7C1394CV18-167BZXC

CY7C1392CV18-167BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1992CV18-167BZI

CY7C1393CV18-167BZI

CY7C1394CV18-167BZI

CY7C1392CV18-167BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1992CV18-167BZXI

CY7C1393CV18-167BZXI

CY7C1394CV18-167BZXI

Page 28 of 30 [+] Feedback

CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B - 01.0665X
11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M N P R
0.15 4X

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1392CV18-200BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1392CV18-200BZC 508013