CY7C1383C-100AC

CY7C1383C-100AC Datasheet

CY7C1381C CY7C1383C

Part	Datasheet
CY7C1383C-100AC	CY7C1383C-100AC (pdf)

Related Parts	Information
CY7C1381C-100AC	CY7C1381C-100AC

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CY7C1381C CY7C1383C 18-Mb 512K x 36/1M x 18 Flow-Through SRAM • Supports 133-MHz bus operations • 512K X 36/1M X 18 common I/O • 3.3V and +10% core power supply VDD • 2.5V or 3.3V I/O supply VDDQ • Fast clock-to-output times ns 133-MHz version ns 117-MHz version ns 100-MHz version • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP ,119-ball BGA and 165-ball fBGA packages • JTAG boundary scan for BGA and fBGA packages • “ZZ” Sleep Mode option Functional Description[1] The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and 1M x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CCoEn1tr o, EW2riatendECnaEb3l[e2]s , BBuWrsxt, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. The CY7C1381C/CY7C1383C allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . The CY7C1381C/CY7C1383C operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 210 70 117 MHz 190 70 100 MHz 175 70 Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable. Unit ns mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C1381C CY7C1383C Logic Block Diagram CY7C1381C 512K x 36 A0, A1, A MODE ADV CLK ADSC ADSP BWD CLK BWCEAN BWE GW CE1 CE2 CE3 OE A0, A1, A MODE C ADDRESS REGISTER A[1:0] BURST Q1 COUNTER AND LOGIC DQD, DQPD BYTE WRITE REGISTER DQD, DQPD BYTE WRITE REGISTER DQC, DQPC BYTE WRITEARDEDGIRSTEESRS Ordering Information Speed MHz Ordering Code CY7C1381C-133AC CY7C1383C-133AC CY7C1381C-133BGC CY7C1383C-133BGC CY7C1381C-133BZC CY7C1383C-133BZC CY7C1381C-117AC CY7C1383C-117AC CY7C1381C-117BGC CY7C1383C-117BGC CY7C1381C-117BZC CY7C1383C-117BZC CY7C1381C-117AI CY7C1383C-117AI CY7C1381C-117BGI CY7C1383C-117BGI CY7C1381C-117BZI CY7C1383C-117BZI High-Z DON’T CARE Package Name Part and Package Type A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables Operating Range Commercial Commercial BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG BB165A A101 BG119 BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG Industrial Page 32 of 36 CY7C1381C CY7C1383C Ordering Information Speed MHz Ordering Code Package Name Part and Package Type 100 CY7C1381C-100AC CY7C1383C-100AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1381C-100BGC CY7C1383C-100BGC BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1381C-100BZC CY7C1383C-100BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG CY7C1381C-100AI CY7C1383C-100AI A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1381C-100BGI CY7C1383C-100BGI BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG CY7C1381C-100BZI CY7C1383C-100BZI BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Operating Range Commercial Industrial Package Diagrams 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 100 1 81 80 DIMENSIONS ARE IN MILLIMETERS. R MIN. MAX. GAUGE PLANE 0° -7° REF. 30 31 0° MIN. R MIN. MAX. MIN. DETAIL A TYP. 51 50 STAND-OFF MIN. MAX. 12° ±1° 8X SEATING PLANE SEE DETAIL MAX. MAX. 51-85050-*A

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CY7C1381C CY7C1383C
18-Mb 512K x 36/1M x 18 Flow-Through SRAM
• Supports 133-MHz bus operations
• 512K X 36/1M X 18 common I/O
• 3.3V and +10% core power supply VDD
• 2.5V or 3.3V I/O supply VDDQ
• Fast clock-to-output times
ns 133-MHz version
ns 117-MHz version
ns 100-MHz version
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP ,119-ball BGA
and 165-ball fBGA packages
• JTAG boundary scan for BGA and fBGA packages
• “ZZ” Sleep Mode option

Functional Description[1]

The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and 1M x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CCoEn1tr o, EW2riatendECnaEb3l[e2]s , BBuWrsxt, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

The CY7C1381C/CY7C1383C allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

The CY7C1381C/CY7C1383C operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
133 MHz 210 70
117 MHz 190 70
100 MHz 175 70

Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Unit ns mA

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C1381C CY7C1383C

Logic Block Diagram CY7C1381C 512K x 36

A0, A1, A

MODE ADV CLK

ADSC ADSP BWD

CLK BWCEAN

BWE GW CE1 CE2 CE3 OE

A0, A1, A

MODE C

ADDRESS REGISTER

A[1:0]

BURST Q1

COUNTER

AND LOGIC

DQD, DQPD BYTE

WRITE REGISTER

DQD, DQPD BYTE

WRITE REGISTER

DQC, DQPC BYTE

WRITEARDEDGIRSTEESRS
Ordering Information

Speed MHz
Ordering Code

CY7C1381C-133AC CY7C1383C-133AC

CY7C1381C-133BGC CY7C1383C-133BGC

CY7C1381C-133BZC CY7C1383C-133BZC

CY7C1381C-117AC

CY7C1383C-117AC

CY7C1381C-117BGC

CY7C1383C-117BGC

CY7C1381C-117BZC CY7C1383C-117BZC

CY7C1381C-117AI CY7C1383C-117AI

CY7C1381C-117BGI CY7C1383C-117BGI

CY7C1381C-117BZI CY7C1383C-117BZI

High-Z

DON’T CARE

Package Name

Part and Package Type

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

Operating Range

Commercial

Commercial

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

BB165A A101 BG119

BB165A
165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG
100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables
119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG
165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

Industrial

Page 32 of 36

CY7C1381C CY7C1383C
Ordering Information

Speed MHz
Ordering Code

Package Name

Part and Package Type
100 CY7C1381C-100AC CY7C1383C-100AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1381C-100BGC CY7C1383C-100BGC

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1381C-100BZC CY7C1383C-100BZC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

CY7C1381C-100AI CY7C1383C-100AI

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1381C-100BGI CY7C1383C-100BGI

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1381C-100BZI CY7C1383C-100BZI

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.

Operating Range

Commercial

Industrial

Package Diagrams
100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101
100 1
81 80

DIMENSIONS ARE IN MILLIMETERS.

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
30 31
0° MIN.

R MIN. MAX.

MIN.

DETAIL A

TYP.
51 50

STAND-OFF MIN. MAX.
12° ±1° 8X

SEATING PLANE

SEE DETAIL

MAX. MAX.
51-85050-*A

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Datasheet ID: CY7C1383C-100AC 508004