CY7C1370DV25-250AXCT

CY7C1370DV25-250AXCT Datasheet

CY7C1370DV25 CY7C1372DV25

Part	Datasheet
CY7C1370DV25-250AXCT	CY7C1370DV25-250AXCT (pdf)

Related Parts	Information
CY7C1370DV25-250AXC	CY7C1370DV25-250AXC

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CY7C1370DV25 CY7C1372DV25 18-Mbit 512 K x 36/1 M x 18 Pipelined SRAM with NoBL Architecture 18-Mbit 512 K x 36/1 M x 18 Pipelined SRAM with NoBL Architecture • Pin-compatible and functionally equivalent to ZBT • Supports 250-MHz bus operations with zero wait states Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered inputs and outputs for pipelined operation • Byte write capability • Single V core power supply VDD • V I/O power supply VDDQ • Fast clock-to-output times ns for 250-MHz device • Clock enable CEN pin to suspend operation • Synchronous self-timed writes • Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 119-ball BGA and 165-ball FBGA packages • IEEE JTAG-Compatible Boundary Scan • Burst or interleaved burst order • “ZZ” sleep mode option and stop clock option Functional Description The CY7C1370DV25 and CY7C1372DV25 are V, 512 K x 36 and 1-Mbit x 18 synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1370DV25 and CY7C1372DV25 are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1370DV25 and CY7C1372DV25 are pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the byte write selects for CY7C1370DV25 and for CY7C1372DV25 and a write enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables CE1, CE2, CE3 and an asynchronous output enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram - CY7C1370DV25 512 K x 36 A0, A1, A MODE ADV/LD BWa BWb BWc BWd ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY O U T P U T R E G I S T E R S E D A T A S T E R I N O U T P U T B U F E R S E INPUT REGISTER 1 E INPUT REGISTER 0 E DQs DQPa DQPb DQPc DQPd READ LOGIC SLEEP CONTROL Read/Write/Timing 21 NOP,STALL and DESELECT Cycles 22 ZZ Mode Timing 22 Ordering Information 23 Ordering Code Definitions 23 Package Diagrams 24 Acronyms 27 Document Conventions 27 Units of Measure 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29 Page 3 of 29 [+] Feedback Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Pin Configurations 250 MHz 350 70 200 MHz 300 70 100-pin TQFP Pinout CY7C1370DV25 CY7C1372DV25 167 MHz Unit 100 A 99 A 98 CE1 97 CE2 96 BWd 95 BWc 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A 100 A 99 A 98 CE1 97 CE2 96 NC 95 NC 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A DQPc 1 DQc 2 DQc 3 VDDQ 4 VSS 5 DQc 6 DQc 7 DQc 8 DQc 9 VDDQ 11 DQc 12 DQc 13 NC 14 VDD 15 VSS 17 DQd 18 DQd 19 VDDQ 20 VSS 21 DQd 22 DQd 23 DQd 24 DQd 25 VSS 26 VDDQ 27 DQd 28 DQd 29 DQPd 30 CY7C1370DV25 512K x 36 80 DQPb NC 1 79 DQb NC 2 78 DQb NC 3 77 VDDQ 4 76 VSS Ordering Information Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 167 CY7C1370DV25-167AXC CY7C1372DV25-167AXC CY7C1370DV25-167BZC 200 CY7C1370DV25-200BZC Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Operating Range Commercial Commercial Ordering Code Definitions CY7C 137X D V25 - XXX XX X Temperature Range X = C or I C = Commercial I = Industrial Package Type XX = AX or BZ AX = 100-pin TQFP Pb-free BZ = 165-ball FPBGA Speed Grade XXX = 167 MHz / 200 MHz / 250 MHz Volt Process Technology 90nm 137X 1370 = PL, 512 Kb x 36 18 Mb 1372 = PL, 1 Mb x 18 Mb CY7C = Cypress SRAMs Page 23 of 29 [+] Feedback CY7C1370DV25 CY7C1372DV25 Package Diagrams Figure 100-pin Thin Plastic Quad Flatpack 14 x 20 x mm , 51-85050 51-85050 C Page 24 of 29 [+] Feedback Figure 119-ball BGA 14 x 22 x mm , 51-85115 CY7C1370DV25 CY7C1372DV25 51-85115 C Page 25 of 29 [+] Feedback CY7C1370DV25 CY7C1372DV25 Figure 165-ball FPBGA 13 x 15 x mm , 51-85180 51-85180 *C Page 26 of 29 [+] Feedback Acronyms Acronym CE CEN FPBGA JTAG NoBL OE SEL TCK TDI TMS TDO TQFP WE Description chip enable clock enable fine-pitch ball grid array Joint Test Action Group No Bus Latency output enable single event latch-up test clock test data input test mode select test data output thin quad flat pack write enable CY7C1370DV25 CY7C1372DV25 Document Conventions Units of Measure Symbol ns V µA mA ms MHz pF W °C Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds Mega Hertz pico Farad Watts degree Celcius Page 27 of 29 [+] Feedback CY7C1370DV25 CY7C1372DV25 Document History Page Document Title CY7C1370DV25/CY7C1372DV25 18-Mbit 512 K x 36/1 M x 18 Pipelined SRAM with NoBL Architecture Document Number 38-05558 ECN No. Issue Date Orig. of Change Description of Change 254509 See ECN RKF New data sheet 288531 See ECN SYT Edited description under “IEEE Serial Boundary Scan JTAG ” for non-compliance with Added comment of ‘Lead-free BG packages availability’ below the Ordering Information 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to and °C/W respectively Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to and °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to and °C/W respectively Modified VOL, VOH test conditions Removed comment of ‘Lead-free BG packages availability’ below the Ordering Information Updated Ordering Information Table 418125 See ECN NXR Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of IX from Input Load Current to Input Leakage Current on page# 18 Changed the IX current values of MODE on page # 18 from uA and 30 uA to uA and 5 uA Changed the IX current values of ZZ on page # 18 from uA and 5 uA to uA and 30 uA Changed VIH < VDD to VIH < VDDon page # 18 Updated Ordering Information Table 475677 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. 2897278 03/22/2010 NJY Removed obsolete part numbers from Ordering Information table and updated package diagrams. 3031731 09/16/2010 NJY Updated Ordering Information and added Ordering Code Definitions Added Acronyms and Units of Measure Minor edits and updated in new template 3050869 10/07/2010 NJY Removed CY7C1370DV25-167BZI, CY7C1370DV25-250AXC, and CY7C1370DV25-167AXI parts from Ordering Information. Page 28 of 29 [+] Feedback CY7C1370DV25 CY7C1372DV25 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 29 of 29 [+] Feedback

PDF Datasheet Preview

CY7C1370DV25 CY7C1372DV25
18-Mbit 512 K x 36/1 M x 18 Pipelined SRAM with NoBL Architecture
18-Mbit 512 K x 36/1 M x 18 Pipelined SRAM with NoBL Architecture
• Pin-compatible and functionally equivalent to ZBT
• Supports 250-MHz bus operations with zero wait states

Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
• Fully registered inputs and outputs for pipelined operation
• Byte write capability
• Single V core power supply VDD
• V I/O power supply VDDQ
• Fast clock-to-output times
ns for 250-MHz device
• Clock enable CEN pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non-Pb-free 119-ball BGA and 165-ball FBGA packages
• IEEE JTAG-Compatible Boundary Scan
• Burst or interleaved burst order
• “ZZ” sleep mode option and stop clock option

Functional Description

The CY7C1370DV25 and CY7C1372DV25 are V, 512 K x 36 and 1-Mbit x 18 synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1370DV25 and CY7C1372DV25 are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1370DV25 and CY7C1372DV25 are pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the byte write selects for CY7C1370DV25 and for CY7C1372DV25 and a write enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous chip enables CE1, CE2, CE3 and an asynchronous output enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

Logic Block Diagram - CY7C1370DV25 512 K x 36

A0, A1, A

MODE

ADV/LD

BWa BWb BWc BWd

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

WRITE DRIVERS

MEMORY

ARRAY

O U T P U T R E G I S T E R S E

D A T A S T E R I N

O U T P U T

B U F E R S E

INPUT REGISTER 1 E

INPUT REGISTER 0 E

DQs DQPa DQPb DQPc DQPd

READ LOGIC

SLEEP

CONTROL
Read/Write/Timing 21 NOP,STALL and DESELECT Cycles 22 ZZ Mode Timing 22 Ordering Information 23 Ordering Code Definitions 23 Package Diagrams 24 Acronyms 27 Document Conventions 27 Units of Measure 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29

Page 3 of 29 [+] Feedback

Selection Guide

Maximum access time Maximum operating current Maximum CMOS standby current

Pin Configurations
250 MHz 350 70
200 MHz 300 70
100-pin TQFP Pinout

CY7C1370DV25 CY7C1372DV25
167 MHz

Unit
100 A 99 A 98 CE1 97 CE2 96 BWd 95 BWc 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A 100 A 99 A 98 CE1 97 CE2 96 NC 95 NC 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A

DQPc 1

DQc 2

DQc 3 VDDQ 4

VSS 5 DQc 6 DQc 7

DQc 8

DQc 9

VDDQ 11

DQc 12

DQc 13

NC 14

VDD 15

VSS 17

DQd 18

DQd 19 VDDQ 20

VSS 21

DQd 22

DQd 23

DQd 24

DQd 25

VSS 26 VDDQ 27

DQd 28

DQd 29

DQPd 30

CY7C1370DV25 512K x 36
80 DQPb NC 1
79 DQb NC 2
78 DQb NC 3
77 VDDQ 4
76 VSS
Ordering Information

Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
167 CY7C1370DV25-167AXC

CY7C1372DV25-167AXC

CY7C1370DV25-167BZC
200 CY7C1370DV25-200BZC

Package Diagram

Part and Package Type
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free
51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial

Commercial
Ordering Code Definitions CY7C 137X D V25 - XXX XX X

Temperature Range X = C or I C = Commercial I = Industrial

Package Type XX = AX or BZ AX = 100-pin TQFP Pb-free BZ = 165-ball FPBGA

Speed Grade XXX = 167 MHz / 200 MHz / 250 MHz

Volt

Process Technology 90nm
137X 1370 = PL, 512 Kb x 36 18 Mb 1372 = PL, 1 Mb x 18 Mb

CY7C = Cypress SRAMs

Page 23 of 29 [+] Feedback

CY7C1370DV25 CY7C1372DV25

Package Diagrams

Figure 100-pin Thin Plastic Quad Flatpack 14 x 20 x mm , 51-85050
51-85050 *C

Page 24 of 29 [+] Feedback

Figure 119-ball BGA 14 x 22 x mm , 51-85115

CY7C1370DV25 CY7C1372DV25
51-85115 *C

Page 25 of 29 [+] Feedback

CY7C1370DV25 CY7C1372DV25

Figure 165-ball FPBGA 13 x 15 x mm , 51-85180
51-85180 *C

Page 26 of 29 [+] Feedback

Acronyms

Acronym CE CEN FPBGA JTAG NoBL OE SEL TCK TDI TMS TDO TQFP WE

Description chip enable clock enable fine-pitch ball grid array Joint Test Action Group No Bus Latency output enable single event latch-up test clock test data input test mode select test data output thin quad flat pack write enable

CY7C1370DV25 CY7C1372DV25

Document Conventions

Units of Measure

Symbol ns V µA mA ms MHz pF W °C

Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds Mega Hertz pico Farad Watts degree Celcius

Page 27 of 29 [+] Feedback

CY7C1370DV25 CY7C1372DV25

Document History Page

Document Title CY7C1370DV25/CY7C1372DV25 18-Mbit 512 K x 36/1 M x 18 Pipelined SRAM with NoBL Architecture Document Number 38-05558

ECN No.

Issue Date

Orig. of Change

Description of Change
254509 See ECN RKF New data sheet
288531 See ECN SYT Edited description under “IEEE Serial Boundary Scan JTAG ” for
non-compliance with
Added comment of ‘Lead-free BG packages availability’ below the Ordering

Information
326078 See ECN

PCI Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard

Added description on EXTEST Output Bus Tri-State

Changed description on the Tap Instruction Set Overview and Extest

Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to and °C/W respectively

Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to and °C/W respectively

Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to and °C/W respectively

Modified VOL, VOH test conditions Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
418125 See ECN NXR Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Changed the description of IX from Input Load Current to Input Leakage Current on page# 18

Changed the IX current values of MODE on page # 18 from uA and 30 uA to uA and 5 uA

Changed the IX current values of ZZ on page # 18 from uA and 5 uA to uA and 30 uA
Changed VIH < VDD to VIH < VDDon page # 18 Updated Ordering Information Table
475677 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

AC Switching Characteristics table.
Updated the Ordering Information table.
2897278 03/22/2010 NJY Removed obsolete part numbers from Ordering Information table and
updated package diagrams.
3031731 09/16/2010 NJY Updated Ordering Information and added Ordering Code Definitions

Added Acronyms and Units of Measure

Minor edits and updated in new template
3050869 10/07/2010 NJY Removed CY7C1370DV25-167BZI, CY7C1370DV25-250AXC, and
CY7C1370DV25-167AXI parts from Ordering Information.

Page 28 of 29 [+] Feedback

CY7C1370DV25 CY7C1372DV25

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 29 of 29
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1370DV25-250AXCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1370DV25-250AXCT 507992