CY7C1368C-166AXC

CY7C1368C-166AXC Datasheet

CY7C1368C

Part	Datasheet
CY7C1368C-166AXC	CY7C1368C-166AXC (pdf)

Related Parts	Information
CY7C1368C-166AXCT	CY7C1368C-166AXCT

PDF Datasheet Preview
CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM • Registered inputs and outputs for pipelined operation • Optimal for performance Double-Cycle deselect Depth expansion without wait state • 256K x 32-bit common I/O architecture • 3.3V core power supply VDD • 2.5V/3.3V I/O power supply VDDQ • Fast clock-to-output times ns for 250-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Multiple chip enables for depth expansion Three chip enables for A package version and Two chip enables for AJ package version • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous Output Enable • Available in JEDEC-standard lead-free 100-Pin TQFP package • “ZZ” Sleep Mode option Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz 250 40 Functional Description[1] The CY7C1368C SRAM integrates 256K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3[2] , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BWA, BWB, BWC, BWD, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penal izing system performance. The CY7C1368C operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. 200 MHz 220 40 166 MHz Unit Notes For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on CE3 is for A version 3 Chip enable option only. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1368C Functional Block Diagram-CY7C1368C 256K x 32 A0,A1,A MODE ADDRESS REGISTER 2 A[1:0] BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BYTE WRITE REGISTER DQD BYTE WRITE DRIVER BYTE WRITE REGISTER DQC BYTE WRITE DRIVER BYTE WRITE REGISTER BYTE Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 166 CY7C1368C-166AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable Commercial CY7C1368C-166AJXC 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable CY7C1368C-166AXI 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable Industrial CY7C1368C-166AJXI 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable 200 CY7C1368C-200AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable Commercial CY7C1368C-200AJXC 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable CY7C1368C-200AXI 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable Industrial CY7C1368C-200AJXI 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable 250 CY7C1368C-250AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable Commercial CY7C1368C-250AJXC 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable CY7C1368C-250AXI 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable Industrial CY7C1368C-250AJXI 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable Page 16 of 18 [+] Feedback Package Diagram 100-Pin TQFP 14 x 20 x mm 51-85050 100 1 81 80 CY7C1368C R MIN. MAX. GAUGE PLANE 0° -7° REF. ordering information table 332879 See ECN PCI Shaded 250 MHz speed bin in the AC/DC Table and Selection Guide Added Address Expansion pins in the Pin Definition Table Modified VOL, VOH test conditions Corrected VDDQ from 2.5V 5% to VDD to 3.3V −5%/+10% on page# 9 Updated Ordering Information Table 377095 See ECN PCI Changed ISB2 from 30 to 40 mA Modified test condition in note# 9 from VIH < VDD to VIH < VDD 408725 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Converted from Preliminary to Final Replaced Package Name column with Package Diagram in the Ordering Information table Updated the ordering information 429278 See ECN NXR Added 2.5VI/O option Updated Ordering Information Table 501828 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Updated the Ordering Information table. Page 18 of 18 [+] Feedback

PDF Datasheet Preview

CY7C1368C
9-Mbit 256K x 32 Pipelined DCD Sync SRAM
• Registered inputs and outputs for pipelined operation
• Optimal for performance Double-Cycle deselect

Depth expansion without wait state
• 256K x 32-bit common I/O architecture
• 3.3V core power supply VDD
• 2.5V/3.3V I/O power supply VDDQ
• Fast clock-to-output times
ns for 250-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting
interleaved or linear burst sequences
• Multiple chip enables for depth expansion Three chip
enables for A package version and Two chip enables for AJ package version
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP package
• “ZZ” Sleep Mode option

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
250 MHz 250 40

Functional Description[1]

The CY7C1368C SRAM integrates 256K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3[2] , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BWA, BWB, BWC, BWD, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penal izing system performance.

The CY7C1368C operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
200 MHz 220 40
166 MHz

Unit

Notes For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on CE3 is for A version 3 Chip enable option only.

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1368C

Functional Block Diagram-CY7C1368C 256K x 32

A0,A1,A

MODE

ADDRESS REGISTER
2 A[1:0]

BURST Q1

COUNTER AND

LOGIC

CLR Q0

ADSC ADSP

BYTE

WRITE REGISTER

DQD BYTE WRITE DRIVER

BYTE

WRITE REGISTER

DQC BYTE WRITE DRIVER

BYTE

WRITE REGISTER

BYTE
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
166 CY7C1368C-166AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable

Commercial

CY7C1368C-166AJXC
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable

CY7C1368C-166AXI
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable

Industrial

CY7C1368C-166AJXI
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable
200 CY7C1368C-200AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable

Commercial

CY7C1368C-200AJXC
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable

CY7C1368C-200AXI
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable

Industrial

CY7C1368C-200AJXI
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable
250 CY7C1368C-250AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable

Commercial

CY7C1368C-250AJXC
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable

CY7C1368C-250AXI
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 3 Chip enable

Industrial

CY7C1368C-250AJXI
100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 2 Chip enable

Page 16 of 18 [+] Feedback

Package Diagram
100-Pin TQFP 14 x 20 x mm 51-85050
100 1
81 80

CY7C1368C

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
ordering information table
332879 See ECN

PCI Shaded 250 MHz speed bin in the AC/DC Table and Selection Guide

Added Address Expansion pins in the Pin Definition Table
Modified VOL, VOH test conditions Corrected VDDQ from 2.5V 5% to VDD to 3.3V −5%/+10% on page# 9 Updated Ordering Information Table
377095 See ECN

PCI Changed ISB2 from 30 to 40 mA

Modified test condition in note# 9 from VIH < VDD to VIH < VDD
408725 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Converted from Preliminary to Final
Replaced Package Name column with Package Diagram in the Ordering Information table
Updated the ordering information
429278 See ECN NXR Added 2.5VI/O option
Updated Ordering Information Table
501828 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Updated the Ordering Information table.

Page 18 of 18 [+] Feedback

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Datasheet ID: CY7C1368C-166AXC 507991