CY7C1365C-133BZI

CY7C1365C-133BZI Datasheet

CY7C1365C

Part	Datasheet
CY7C1365C-133BZI	CY7C1365C-133BZI (pdf)

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CY7C1365C 9-Mbit 256 K x 32 Flow-Through Sync SRAM 9-Mbit 256 K x 32 Flow-Through Sync SRAM • 256 K x 32 common I/O • V core power supply VDD • V/3.3 V I/O power supply VDDQ • Fast clock-to-output times ns 133-MHz version • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Supports V I/O level • Available in 165-Ball FBGA package • “ZZ” Sleep Mode option • IEEE JTAG-compatible boundary scan Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current Functional Description The CY7C1365C is a 256 K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BW[A:D], and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. The CY7C1365C allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and Chip Enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . The CY7C1365C operates from a V core power supply while all outputs may operate with either a or V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. 133 MHz Unit • San Jose, CA 95134-1709 • 408-943-2600 Logic Block Diagram CY7C1365C A0, A1, A MODE ADV CLK ADSC ADSP BWD BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A[1:0] BURST Q1 COUNTER AND LOGIC DQD BYTE WRITE REGISTER DQC BYTE WRITE REGISTER DQB BYTE WRITE REGISTER DQA BYTE WRITE REGISTER ENABLE REGISTER SLEEP CONTROL CY7C1365C DQD BYTE WRITE REGISTER DQC BYTE WRITE REGISTER DQB BYTE WRITE REGISTER DQA BYTE WRITE REGISTER MEMORY ARRAY OUTPUT SENSE BUFFERS AMPS INPUT REGISTERS Page 2 of 30 CY7C1365C TAP DC Electrical Characteristics and Operating Conditions 16 Identification Register Definitions 16 Scan Register Sizes 16 Instruction Codes 17 Boundary Scan Order 18 Maximum Ratings 19 Operating Range 19 Electrical Characteristics 19 Capacitance 20 Thermal Resistance 20 AC Test Loads and Waveforms 20 Switching Characteristics 21 Timing Diagrams 22 Ordering Information 26 Ordering Code Definitions 26 Package Diagram 27 Acronyms 28 Document Conventions 28 Units of Measure 28 Document History Page 29 Sales, Solutions, and Legal Information 30 Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30 Page 3 of 30 CY7C1365C Pin Configurations A NC/288M A B NC/144M A VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ NC/72M A R MODE NC/36M A Figure 165-ball FBGA pinout CY7C1365C 256 K x 32 BWC BWD VSS VDD VDD VSS BWB BWA VSS VSS NC CE3 CLK VSS NC/18M VSS NC A0 TCK ADSC VSS VDD VSS ADSP VDDQ NC VDDQ A NC/576M NC/1G NC DQB NC DQB ZZ DQA NC DQA NC Page 4 of 30 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 133 CY7C1365C-133BZI 51-85180 165-ball FBGA 13 x 15 x mm Industrial Ordering Code Definitions CY 7 C 1365 C - 133 BZ X I Temperature range I = Industrial = °C to +85 °C X = Pb-free Package Type A = 165-ball FBGA Speed Grade 133 MHz Process Technology C 90 nm Part Identifier 1365 = DCD, 256 K x 32 9 Mb Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Page 26 of 30 CY7C1365C Package Diagram Figure 165-ball FBGA 13 x 15 x mm BB165D/BW165D Ball Diameter Package Outline, 51-85180 51-85180 *F Page 27 of 30 Acronyms Acronym chip enable CMOS complementary metal-oxide-semiconductor electronic industries alliance FBGA fine-pitch ball grid array input/output JEDEC joint electron devices engineering council JTAG joint test action group least significant bit most significant bit output enable SRAM static random access memory test access port test clock test data-in test data-out test mode select transistor-transistor logic CY7C1365C Document Conventions Units of Measure Symbol °C MHz µA µs mA mm ms mV ns % pF V W Unit of Measure degree Celsius megahertz microampere microsecond milliampere millimeter millisecond millivolt nanosecond ohm percent picofarad volt watt Page 28 of 30 CY7C1365C Document History Page Document Title CY7C1365C, 9-Mbit 256 K x 32 Flow-Through Sync SRAM Document Number 001-74584

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CY7C1365C
9-Mbit 256 K x 32 Flow-Through Sync SRAM
9-Mbit 256 K x 32 Flow-Through Sync SRAM
• 256 K x 32 common I/O
• V core power supply VDD
• V/3.3 V I/O power supply VDDQ
• Fast clock-to-output times
ns 133-MHz version
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports V I/O level
• Available in 165-Ball FBGA package
• “ZZ” Sleep Mode option
• IEEE JTAG-compatible boundary scan

Selection Guide

Maximum Access Time Maximum Operating Current Maximum Standby Current

Functional Description

The CY7C1365C is a 256 K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BW[A:D], and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. The CY7C1365C allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and Chip Enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . The CY7C1365C operates from a V core power supply while all outputs may operate with either a or V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
133 MHz Unit
• San Jose, CA 95134-1709
• 408-943-2600

Logic Block Diagram CY7C1365C

A0, A1, A MODE ADV CLK

ADSC ADSP BWD

BWA BWE

GW CE1 CE2 CE3 OE

ADDRESS REGISTER

A[1:0]

BURST Q1

COUNTER

AND LOGIC

DQD BYTE WRITE REGISTER

DQC BYTE WRITE REGISTER

DQB BYTE WRITE REGISTER

DQA BYTE WRITE REGISTER

ENABLE REGISTER

SLEEP CONTROL

CY7C1365C

DQD BYTE WRITE REGISTER

DQC BYTE WRITE REGISTER

DQB BYTE WRITE REGISTER

DQA BYTE WRITE REGISTER

MEMORY ARRAY

OUTPUT

SENSE

BUFFERS

AMPS

INPUT REGISTERS

Page 2 of 30

CY7C1365C
TAP DC Electrical Characteristics and Operating Conditions 16 Identification Register Definitions 16 Scan Register Sizes 16 Instruction Codes 17 Boundary Scan Order 18 Maximum Ratings 19 Operating Range 19 Electrical Characteristics 19 Capacitance 20 Thermal Resistance 20 AC Test Loads and Waveforms 20 Switching Characteristics 21 Timing Diagrams 22 Ordering Information 26
Ordering Code Definitions 26 Package Diagram 27 Acronyms 28 Document Conventions 28

Units of Measure 28 Document History Page 29 Sales, Solutions, and Legal Information 30

Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30

Page 3 of 30

CY7C1365C

Pin Configurations

A NC/288M A

B NC/144M A

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

NC/72M A

R MODE NC/36M A

Figure 165-ball FBGA pinout

CY7C1365C 256 K x 32

BWC BWD VSS VDD

VDD VSS

BWB BWA VSS

VSS NC

CE3 CLK

VSS NC/18M

VSS NC

A0 TCK

ADSC

VSS VDD VSS

ADSP VDDQ

NC VDDQ

A NC/576M

NC/1G NC

DQB NC

DQB ZZ

DQA NC

DQA NC

Page 4 of 30
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
133 CY7C1365C-133BZI
51-85180 165-ball FBGA 13 x 15 x mm

Industrial
Ordering Code Definitions CY 7 C 1365 C - 133 BZ X I

Temperature range I = Industrial = °C to +85 °C X = Pb-free Package Type A = 165-ball FBGA Speed Grade 133 MHz Process Technology C 90 nm Part Identifier 1365 = DCD, 256 K x 32 9 Mb Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress

Page 26 of 30

CY7C1365C

Package Diagram

Figure 165-ball FBGA 13 x 15 x mm BB165D/BW165D Ball Diameter Package Outline, 51-85180
51-85180 *F

Page 27 of 30

Acronyms

Acronym
chip enable

CMOS
complementary metal-oxide-semiconductor
electronic industries alliance

FBGA
fine-pitch ball grid array
input/output

JEDEC joint electron devices engineering council

JTAG
joint test action group
least significant bit
most significant bit
output enable

SRAM
static random access memory
test access port
test clock
test data-in
test data-out
test mode select
transistor-transistor logic

CY7C1365C

Document Conventions

Units of Measure

Symbol °C MHz µA µs mA mm ms mV ns
% pF V W

Unit of Measure degree Celsius megahertz microampere microsecond milliampere millimeter millisecond millivolt nanosecond ohm percent picofarad volt watt

Page 28 of 30

CY7C1365C

Document History Page

Document Title CY7C1365C, 9-Mbit 256 K x 32 Flow-Through Sync SRAM Document Number 001-74584

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1365C-133BZI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1365C-133BZI 507990