CY7C1360B-166BGC

CY7C1360B-166BGC Datasheet

CY7C1360B CY7C1362B

Part	Datasheet
CY7C1360B-166BGC	CY7C1360B-166BGC (pdf)

Related Parts	Information
CY7C1362B-166AJC	CY7C1362B-166AJC
CY7C1362B-166BGC	CY7C1362B-166BGC

PDF Datasheet Preview
CY7C1360B CY7C1362B 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] • Supports bus operation up to 225 MHz • Available speed grades are 225, 200 and 166 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times ns for 225-MHz device ns for 200-MHz device ns for 166-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages • TQFP Available with 3-Chip Enable and 2-Chip Enable • IEEE JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1360B/CY7C1362B SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, WD COSrhiEtPipe , and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to two or four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1360B/CY7C1362B operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 225 MHz 200 MHz 166 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on CE3 is for A version of TQFP 3 Chip Enable option and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable. Unit ns mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Logic Block DiagrC1360B 256K x 36 A0, A1, A MODE ADV CLK ADSC ADSP BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A[1:0] BURST COUNTER CLR AND Q0 LOGIC DQD ,DQPD BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE DQD ,DQPD BYTE Ordering Information Speed MHz Ordering Code Package Name Part and Package Type 225 CY7C1360B-225AC CY7C1362B-225AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1360B-225AI CY7C1362B-225AI CY7C1360B-225AJC CY7C1362B-225AJC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables CY7C1360B-225AJI CY7C1362B-225AJI CY7C1360B-225BGC CY7C1362B-225BGC BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables and JTAG CY7C1360B-225BGI CY7C1362B-225BGI CY7C1360B-225BZC CY7C1362B-225BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG CY7C1360B-225BZI CY7C1362B-225BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Page 29 of 34 CY7C1360B CY7C1362B Ordering Information continued Speed MHz Ordering Code Package Name Part and Package Type 200 CY7C1360B-200AC CY7C1362B-200AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1360B-200AI CY7C1362B-200AI CY7C1360B-200AJC CY7C1362B-200AJC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables CY7C1360B-200AJI CY7C1362B-200AJI CY7C1360B-200BGC CY7C1362B-200BGC BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables and JTAG CY7C1360B-200BGI CY7C1362B-200BGI CY7C1360B-200BZC CY7C1362B-200BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG CY7C1360B-200BZI CY7C1362B-200BZI 166 CY7C1360B-166AC CY7C1362B-166AC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables CY7C1360B-166AI CY7C1362B-166AI CY7C1360B-166AJC CY7C1362B-166AJC A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables CY7C1360B-166AJI CY7C1362B-166AJI CY7C1360B-166BGC CY7C1362B-166BGC BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables and JTAG CY7C1360B-166BGI ICY7C1362B-166BGI CY7C1360B-166BZC CY7C1362B-166BZC BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG CY7C1360B-166BZI CY7C1362B-166BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial VBL Update Ordering Info section shade S,E part numbers Page 34 of 34

PDF Datasheet Preview

CY7C1360B CY7C1362B
9-Mbit 256K x 36/512K x 18 Pipelined SRAM

Functional Description[1]
• Supports bus operation up to 225 MHz
• Available speed grades are 225, 200 and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
ns for 225-MHz device ns for 200-MHz device ns for 166-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option

The CY7C1360B/CY7C1362B SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, WD COSrhiEtPipe , and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to two or four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1360B/CY7C1362B operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide
225 MHz
200 MHz
166 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on CE3 is for A version of TQFP 3 Chip Enable option and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

Unit ns mA

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

Logic Block DiagrC1360B 256K x 36

A0, A1, A

MODE ADV CLK

ADSC ADSP

BWA BWE GW

CE1 CE2 CE3 OE

ADDRESS REGISTER

A[1:0]

BURST COUNTER CLR AND Q0

LOGIC

DQD ,DQPD BYTE

WRITE REGISTER

DQC ,DQPC BYTE

WRITE REGISTER

DQB ,DQPB BYTE

WRITE REGISTER

DQA ,DQPA BYTE

WRITE REGISTER

ENABLE REGISTER

PIPELINED ENABLE

DQD ,DQPD BYTE
Ordering Information

Speed MHz
Ordering Code

Package Name

Part and Package Type
225 CY7C1360B-225AC CY7C1362B-225AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1360B-225AI CY7C1362B-225AI

CY7C1360B-225AJC CY7C1362B-225AJC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables

CY7C1360B-225AJI

CY7C1362B-225AJI

CY7C1360B-225BGC CY7C1362B-225BGC

BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables and JTAG

CY7C1360B-225BGI

CY7C1362B-225BGI

CY7C1360B-225BZC CY7C1362B-225BZC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

CY7C1360B-225BZI

CY7C1362B-225BZI

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.

Operating Range

Commercial Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Page 29 of 34

CY7C1360B CY7C1362B
Ordering Information continued

Speed MHz
Ordering Code

Package Name

Part and Package Type
200 CY7C1360B-200AC CY7C1362B-200AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1360B-200AI CY7C1362B-200AI

CY7C1360B-200AJC CY7C1362B-200AJC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables

CY7C1360B-200AJI

CY7C1362B-200AJI

CY7C1360B-200BGC CY7C1362B-200BGC

BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables and JTAG

CY7C1360B-200BGI

CY7C1362B-200BGI

CY7C1360B-200BZC CY7C1362B-200BZC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

CY7C1360B-200BZI

CY7C1362B-200BZI
166 CY7C1360B-166AC CY7C1362B-166AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1360B-166AI

CY7C1362B-166AI

CY7C1360B-166AJC CY7C1362B-166AJC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables

CY7C1360B-166AJI

CY7C1362B-166AJI

CY7C1360B-166BGC CY7C1362B-166BGC

BG119 119-ball 14 x 22 x mm BGA 2 Chip Enables and JTAG

CY7C1360B-166BGI

ICY7C1362B-166BGI

CY7C1360B-166BZC CY7C1362B-166BZC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

CY7C1360B-166BZI

CY7C1362B-166BZI

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.

Operating Range

Commercial Industrial

Commercial Industrial

Commercial Industrial

Commercial Industrial

Commercial Industrial
VBL Update Ordering Info section shade S,E part numbers

Page 34 of 34

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Datasheet ID: CY7C1360B-166BGC 507987