CY7C1360A-150BGC

CY7C1360A-150BGC Datasheet

CY7C1360A CY7C1362A

Part	Datasheet
CY7C1360A-150BGC	CY7C1360A-150BGC (pdf)

PDF Datasheet Preview
CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM • Fast access times ns, ns, and ns • Fast clock speed 225, 200, 166, and 150 MHz • Fast OE access times ns, ns, and ns • Optimal for depth expansion one cycle chip deselect to eliminate bus contention • 3.3V and +10% power supply • 3.3V or 2.5V I/O supply • 5V-tolerant inputs except I/Os • Clamp diodes to VSS at all inputs and outputs • Common data inputs and data outputs • Byte Write Enable and Global Write control • Multiple chip enables for depth expansion: three chip enables for A package version and two chip enables for BG and AJ package versions • Address pipeline capability • Address, data, and control registers • Internally self-timed Write Cycle • Burst control pins interleaved or linear burst sequence • Automatic power-down feature available using ZZ mode or CE deselect • JTAG boundary scan for BG and AJ package version • Low-profile 119-bump, 14-mm x 22-mm PBGA Ball Grid Array and 100-pin TQFP packages Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs integrate 262,144 x 36 and 524,288 x 18 SRAM cells with advanced Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 7C1360A-225 7C1362A-225 synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE , depth-expansion Chip Enables CE2 and CE3 , burst control inputs ADSC, ADSP, and ADV , Write Enables BWa, BWb, BWc, BWd, and BWE , and global Write GW . However, the CE3 chip enable input is only available for the TA package version. Asynchronous inputs include the Output Enable OE and burst mode control MODE . The data outputs Q , enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor ADSP or Address Status Controller ADSC input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin ADV . Address, data inputs, and Write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the Write control inputs. Individual byte Write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BWb, BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The x18 version only has 18 data inputs/outputs DQa and DQb along with BWa and BWb no BWc, BWd, DQc, and DQd . For the BGA and TQFP AJ package versions, four pins are used to implement JTAG test capabilities Test Mode Select TMS , Test Data-In TDI , Test Clock TCK , and Test Data-Out TDO . The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. The CY7C1360A and CY7C1362A operate from a +3.3V power supply. All inputs and outputs are LVTTL-compatible. 7C1360A-200 7C1362A-200 7C1360A-166 7C1362A-166 7C1360A-150 7C1362A-150 Unit Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 CY7C1360A CY7C1362A Functional Block x 36[1] BBWWaa BBWWEE CLKCLK BBWWbb GWGW BBWWc c BYTE a WRITE BYTE b WRITE BYTE c WRITE BBWWdd BYTE d WRITE byte d write byte c write byte b write byte a write CEC1E CEC2E2 [2] CCEE32 OEOE ZZ AADDSSPP AA AADDSSCC ENABLE Power Down Logic Address Register Input Register AADDVV AA0-1A-A10 MMOODDEE Ordering Information Speed MHz 225 200 166 150 225 200 166 150 200 166 150 200 166 150 Ordering Code CY7C1360A-225AJC CY7C1360A-225AC CY7C1360A-225BGC CY7C1360A-200AJC CY7C1360A-200AC CY7C1360A-200BGC CY7C1360A-166AJC CY7C1360A-166AC CY7C1360A-166BGC CY7C1360A-150AJC CY7C1360A-150AC CY7C1360A-150BGC CY7C1362A-225AJC CY7C1362A-225AC CY7C1362A-225BGC CY7C1362A-200AJC CY7C1362A-200AC CY7C1362A-200BGC CY7C1362A-166AJC CY7C1362A-166AC CY7C1362A-166BGC CY7C1362A-150AJC CY7C1362A-150AC CY7C1362A-150BGC CY7C1360A-200AJI CY7C1360A-200AI CY7C1360A-200BGI CY7C1360A-166AJI CY7C1360A-166AI CY7C1360A-166BGI CY7C1360A-150AJI CY7C1360A-150AI CY7C1360A-150BGI CY7C1362A-200AJI CY7C1362A-200AI CY7C1362A-200BGI CY7C1362A-166AJI CY7C1362A-166AI CY7C1362A-166BGI CY7C1362A-150AJI CY7C1362A-150AI CY7C1362A-150BGI CY7C1360A CY7C1362A Package Name A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 Package Type 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm Operating Range Commercial Commercial Industrial Industrial Page 25 of 28 Package Diagrams 100-pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 CY7C1360A CY7C1362A 51-85050-A Page 26 of 28 Package Diagrams continued 119-Lead BGA 14 x 22 x BG119 CY7C1360A CY7C1362A 51-85115-A Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Page 27 of 28 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1360A CY7C1362A Document Title:CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Document Number 38-05258 ECN No. Issue Date Orig. of Change Description of Change 113846 05/22/02 GLC Change from Spec. 38-00990 to 38-05258 116062 05/28/02 BRI Removed GVT part numbers from title and body of data sheet Added note 19 pg. 19 regarding VCC on “Power On” 116765 09/09/02 BRI Updated package type names on page 3 ICC, ISB3, and ISB4 values corrected on page 19 123144 01/18/03 RBI Updated power-up requirements in Operating Range and in AC Test Loads and Waveforms. Page 28 of 28

PDF Datasheet Preview

CY7C1360A CY7C1362A
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM
• Fast access times ns, ns, and ns
• Fast clock speed 225, 200, 166, and 150 MHz
• Fast OE access times ns, ns, and ns
• Optimal for depth expansion one cycle chip deselect
to eliminate bus contention
• 3.3V and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V-tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for A package version and two chip enables for BG and AJ package versions
• Address pipeline capability
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins interleaved or linear burst sequence
• Automatic power-down feature available using ZZ mode or CE deselect
• JTAG boundary scan for BG and AJ package version
• Low-profile 119-bump, 14-mm x 22-mm PBGA Ball Grid Array and 100-pin TQFP packages

Functional Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.

The CY7C1360A and CY7C1362A SRAMs integrate 262,144 x 36 and 524,288 x 18 SRAM cells with advanced

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
7C1360A-225 7C1362A-225
synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE , depth-expansion Chip Enables CE2 and CE3 , burst control inputs ADSC, ADSP, and ADV , Write Enables BWa, BWb, BWc, BWd, and BWE , and global Write GW . However, the CE3 chip enable input is only available for the TA package version.

Asynchronous inputs include the Output Enable OE and burst mode control MODE . The data outputs Q , enabled by OE, are also asynchronous.

Addresses and chip enables are registered with either Address Status Processor ADSP or Address Status Controller ADSC input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin ADV .

Address, data inputs, and Write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the Write control inputs. Individual byte Write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BWb, BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The x18 version only has 18 data inputs/outputs DQa and DQb along with BWa and BWb no BWc, BWd, DQc, and DQd .

For the BGA and TQFP AJ package versions, four pins are used to implement JTAG test capabilities Test Mode Select TMS , Test Data-In TDI , Test Clock TCK , and Test Data-Out TDO . The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability.

The CY7C1360A and CY7C1362A operate from a +3.3V power supply. All inputs and outputs are LVTTL-compatible.
7C1360A-200 7C1362A-200
7C1360A-166 7C1362A-166
7C1360A-150 7C1362A-150 Unit

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600

CY7C1360A CY7C1362A

Functional Block x 36[1]

BBWWaa BBWWEE CLKCLK

BBWWbb

GWGW BBWWc c

BYTE a WRITE

BYTE b WRITE

BYTE c WRITE

BBWWdd

BYTE d WRITE
byte d write byte c write byte b write byte a write

CEC1E CEC2E2 [2] CCEE32 OEOE ZZ

AADDSSPP AA

AADDSSCC

ENABLE

Power Down Logic

Address Register

Input Register

AADDVV AA0-1A-A10

MMOODDEE
Ordering Information

Speed MHz
225 200 166 150 225 200 166 150 200 166 150 200 166 150
Ordering Code CY7C1360A-225AJC CY7C1360A-225AC CY7C1360A-225BGC CY7C1360A-200AJC CY7C1360A-200AC CY7C1360A-200BGC CY7C1360A-166AJC CY7C1360A-166AC CY7C1360A-166BGC CY7C1360A-150AJC CY7C1360A-150AC CY7C1360A-150BGC CY7C1362A-225AJC CY7C1362A-225AC CY7C1362A-225BGC CY7C1362A-200AJC CY7C1362A-200AC CY7C1362A-200BGC CY7C1362A-166AJC CY7C1362A-166AC CY7C1362A-166BGC CY7C1362A-150AJC CY7C1362A-150AC CY7C1362A-150BGC CY7C1360A-200AJI CY7C1360A-200AI CY7C1360A-200BGI CY7C1360A-166AJI CY7C1360A-166AI CY7C1360A-166BGI CY7C1360A-150AJI CY7C1360A-150AI CY7C1360A-150BGI CY7C1362A-200AJI CY7C1362A-200AI CY7C1362A-200BGI CY7C1362A-166AJI CY7C1362A-166AI CY7C1362A-166BGI CY7C1362A-150AJI CY7C1362A-150AI CY7C1362A-150BGI

CY7C1360A CY7C1362A

Package Name A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119

Package Type 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100-Lead 14 x 20 x mm Thin Quad Flat Pack 119-Lead BGA 14 x 22 x mm

Operating Range

Commercial

Commercial

Industrial

Industrial

Page 25 of 28

Package Diagrams
100-pin Thin Plastic Quad Flatpack 14 x 20 x mm A101

CY7C1360A CY7C1362A
51-85050-*A

Page 26 of 28

Package Diagrams continued
119-Lead BGA 14 x 22 x BG119

CY7C1360A CY7C1362A
51-85115-*A

Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 27 of 28

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1360A CY7C1362A

Document Title:CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Document Number 38-05258

ECN No.

Issue Date

Orig. of Change

Description of Change
113846 05/22/02

GLC Change from Spec. 38-00990 to 38-05258
116062 05/28/02

BRI Removed GVT part numbers from title and body of data sheet

Added note 19 pg. 19 regarding VCC on “Power On”
116765 09/09/02

BRI Updated package type names on page 3

ICC, ISB3, and ISB4 values corrected on page 19
123144 01/18/03

RBI Updated power-up requirements in Operating Range and in AC Test Loads
and Waveforms.

Page 28 of 28

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Datasheet ID: CY7C1360A-150BGC 507986