CY7C1354B-166BGC

CY7C1354B-166BGC Datasheet

CY7C1354B CY7C1356B

Part	Datasheet
CY7C1354B-166BGC	CY7C1354B-166BGC (pdf)

PDF Datasheet Preview
CY7C1354B CY7C1356B 9-Mb 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description • Pin-compatible and functionally equivalent to ZBT • Supports 225-MHz bus operations with zero wait states Available speed grades are 225, 200, and 166 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered inputs and outputs for pipelined op- eration • Byte Write capability • Separate VDDQ for 3.3V or 2.5V I/O • Single 3.3V power supply • Fast clock-to-output times ns for 225-MHz device 3.2ns for 200-MHz device ns for 166-MHz device • Clock Enable CEN pin to suspend operation • Synchronous self-timed writes • Available in 100 TQFP, 119 BGA, and 165 fBGA packages • IEEE JTAG Boundary Scan • Burst or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B are equipped with the advanced NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1354B and CY7C1356B are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects for CY7C1354B and for CY7C1356B and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram-CY7C1354B 256K x 36 A0, A1, A MODE ADV/LD BWa BWb BWc BWd ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY O U T P U T R E G I S T E R S E D A T A S T E R I N O U T P U T B U F E R S E INPUT REGISTER 1 E INPUT REGISTER 0 E DQs DQPa DQPb DQPc DQPd READ LOGIC SLEEP CONTROL Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Ordering Information Speed MHz Ordering Code CY7C1354B-225AC CY7C1356B-225AC CY7C1354B-225AI CY7C1356B-225AI CY7C1354B-225BGC CY7C1356B-225BGC CY7C1354B-225BGI CY7C1356B-225BGI CY7C1354B-225BZC CY7C1356B-225BZC CY7C1354B-225BZI CY7C1356B-225BZI Package Name Package Type A101 100-lead Thin Quad Flat Pack 14 x 20 x mm Operating Range Commercial A101 100-lead Thin Quad Flat Pack 14 x 20 x mm Industrial BG119 119-ball Grid Array 14 x 22 x mm Commercial BG119 119-ball Grid Array 14 x 22 x mm Industrial BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial Page 24 of 29 CY7C1354B CY7C1356B Ordering Information Speed MHz Ordering Code CY7C1354B-200AC CY7C1356B-200AC CY7C1354B-200AI CY7C1356B-200AI CY7C1354B-200BGC CY7C1356B-200BGC CY7C1354B-200BGI CY7C1356B-200BGI CY7C1354B-200BZC CY7C1356B-200BZC CY7C1354B-200BZI CY7C1356B-200BZI CY7C1354B-166AC CY7C1356B-166AC CY7C1354B-166AI CY7C1356B-166AI CY7C1354B-166BGC CY7C1356B-166BGC CY7C1354B-166BGI CY7C1356B-166BGI CY7C1354B-166BZC CY7C1356B-166BZC CY7C1354B-166BZI CY7C1356B-166BZI Package Name Package Type A101 100-lead Thin Quad Flat Pack 14 x 20 x mm A101 100-lead Thin Quad Flat Pack 14 x 20 x mm BG119 119-ball Grid Array 14 x 22 x mm BG119 119-ball Grid Array 14 x 22 x mm BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm A101 100-lead Thin Quad Flat Pack 14 x 20 x mm A101 100-lead Thin Quad Flat Pack 14 x 20 x mm BG119 119-ball Grid Array 14 x 22 x mm BG119 119-ball Grid Array 14 x 22 x mm BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Page 25 of 29 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagrams 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 100 1 81 80 DIMENSIONS ARE IN MILLIMETERS. CY7C1354B CY7C1356B R MIN. MAX. GAUGE PLANE 0° -7° REF. 30 31 0° MIN. R MIN. MAX. MIN. DETAIL A TYP. Added tPower specification Changed footnotes ordering Added Industrial operating range Changed Capacitance table to have TQFP, BGA, and fBGA columns. 205060 See ECN Removed footnote 13 “Minimum voltage equals for pulse durations of less than 20 ns.” Removed footnote 14 “TA is the case temperature.” Changed footnote 15 from “Overshoot VIH AC < VDD + 1.5V for t < tTCYC/2 undershoot: VIL AC < 0.5V for t < tTCYC/2 power-up VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. “to footnote 13“Overshoot VIH AC < VDD +1.5V Pulse width less than tCYC/2 , undershoot VIL AC > -2V Pulse width less than tCYC/2 . “ Added footnote 14 “TPower-up Assumes a linear ramp from 0V to VDD min. within 200ms. During this time VIH < VDD and VDDQ < VDD. “ Added footnote 20 “Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.” Changed footnote 21 from “Test conditions shown in a , b and c of AC Test Loads. “to “Test conditions shown in a of AC Test Loads unless otherwise noted. “ Updated ZZ Mode Electrical Characteristics. Updated ISB1 and ISB3 currents in Electrical Characteristics table. Modified functional block diagram. Modified Truth Table and Write Cycle Descriptions. Updated Ordering Information. 230388 See ECN VBL Modified ID code Changed balls B4 and A5 from BWd and BWb to NC and ball A4 from BWc to BWb for 165-ball FBGA package for CY7C1356B Changed balls C11 from DQPb to DQPa and balls D11,E11,F11 and G11 from DQb to DQa for CY7C1356B. Update Ordering Info section changed BZC to BZI in Industrial part Page 29 of 29

PDF Datasheet Preview

CY7C1354B CY7C1356B
9-Mb 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture

Functional Description
• Pin-compatible and functionally equivalent to ZBT
• Supports 225-MHz bus operations with zero wait states

Available speed grades are 225, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered inputs and outputs for pipelined op-
eration
• Byte Write capability
• Separate VDDQ for 3.3V or 2.5V I/O
• Single 3.3V power supply
• Fast clock-to-output times
ns for 225-MHz device 3.2ns for 200-MHz device ns for 166-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packages
• IEEE JTAG Boundary Scan
• Burst or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option

The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B are equipped with the advanced NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1354B and CY7C1356B are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects for CY7C1354B and for CY7C1356B and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

Logic Block Diagram-CY7C1354B 256K x 36

A0, A1, A

MODE

ADV/LD

BWa BWb BWc BWd

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

WRITE DRIVERS

MEMORY

ARRAY

O U T P U T R E G I S T E R S E

D A T A S T E R I N

O U T P U T

B U F E R S E

INPUT REGISTER 1 E

INPUT REGISTER 0 E

DQs DQPa DQPb DQPc DQPd

READ LOGIC

SLEEP

CONTROL

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600
Ordering Information

Speed MHz
Ordering Code CY7C1354B-225AC CY7C1356B-225AC CY7C1354B-225AI CY7C1356B-225AI CY7C1354B-225BGC CY7C1356B-225BGC CY7C1354B-225BGI CY7C1356B-225BGI CY7C1354B-225BZC CY7C1356B-225BZC CY7C1354B-225BZI CY7C1356B-225BZI

Package Name

Package Type

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm

Operating Range

Commercial

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm

Industrial

BG119 119-ball Grid Array 14 x 22 x mm

Commercial

BG119 119-ball Grid Array 14 x 22 x mm

Industrial

BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial

BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial

Page 24 of 29

CY7C1354B CY7C1356B
Ordering Information

Speed MHz
Ordering Code CY7C1354B-200AC CY7C1356B-200AC CY7C1354B-200AI CY7C1356B-200AI CY7C1354B-200BGC CY7C1356B-200BGC CY7C1354B-200BGI CY7C1356B-200BGI CY7C1354B-200BZC CY7C1356B-200BZC CY7C1354B-200BZI CY7C1356B-200BZI CY7C1354B-166AC CY7C1356B-166AC CY7C1354B-166AI CY7C1356B-166AI CY7C1354B-166BGC CY7C1356B-166BGC CY7C1354B-166BGI CY7C1356B-166BGI CY7C1354B-166BZC CY7C1356B-166BZC CY7C1354B-166BZI CY7C1356B-166BZI

Package Name

Package Type

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm

BG119 119-ball Grid Array 14 x 22 x mm

BG119 119-ball Grid Array 14 x 22 x mm

BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm

BG119 119-ball Grid Array 14 x 22 x mm

BG119 119-ball Grid Array 14 x 22 x mm

BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

BB165A 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Operating Range

Commercial Industrial

Commercial Industrial

Commercial Industrial

Commercial Industrial

Commercial Industrial

Commercial Industrial

Page 25 of 29

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams
100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101
100 1
81 80

DIMENSIONS ARE IN MILLIMETERS.

CY7C1354B CY7C1356B

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
30 31
0° MIN.

R MIN. MAX.

MIN.

DETAIL A

TYP.
Added tPower specification Changed footnotes ordering

Added Industrial operating range

Changed Capacitance table to have TQFP, BGA, and fBGA columns.
205060 See ECN

Removed footnote 13 “Minimum voltage equals for pulse durations of less than 20 ns.”

Removed footnote 14 “TA is the case temperature.”

Changed footnote 15 from “Overshoot VIH AC < VDD + 1.5V for t < tTCYC/2 undershoot:

VIL AC < 0.5V for t < tTCYC/2 power-up VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <
200 ms. “to footnote 13“Overshoot VIH AC < VDD +1.5V Pulse width less than tCYC/2 ,
undershoot VIL AC > -2V Pulse width less than tCYC/2 . “

Added footnote 14 “TPower-up Assumes a linear ramp from 0V to VDD min. within 200ms. During this time VIH < VDD and VDDQ < VDD. “

Added footnote 20 “Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when

VDDQ = 2.5V.”

Changed footnote 21 from “Test conditions shown in a , b and c of AC Test Loads. “to
“Test conditions shown in a of AC Test Loads unless otherwise noted. “

Updated ZZ Mode Electrical Characteristics.

Updated ISB1 and ISB3 currents in Electrical Characteristics table. Modified functional block diagram.

Modified Truth Table and Write Cycle Descriptions.
Updated Ordering Information.
230388 See ECN

VBL Modified ID code

Changed balls B4 and A5 from BWd and BWb to NC and ball A4 from BWc to BWb for 165-ball FBGA package for CY7C1356B Changed balls C11 from DQPb to DQPa and balls D11,E11,F11 and G11
from DQb to DQa for CY7C1356B.
Update Ordering Info section changed BZC to BZI in Industrial part

Page 29 of 29

More datasheets: 4656VX-817 | 4600VX-820 | 80289716 | M39260 SL001 | M39260 SL005 | M39260 SL002 | AD9279BBCZ | AD9279-65EBZ | AD9279-80KITZ | 50216-B002PL

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1354B-166BGC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1354B-166BGC 507982