AD9279BBCZ

AD9279BBCZ Datasheet


AD9279

Part Datasheet
AD9279BBCZ AD9279BBCZ AD9279BBCZ (pdf)
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Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator

AD9279
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator Low power 141 mW per channel, TGC mode, 40 MSPS 60 mW per channel, CW mode 10 mm x 10 mm, 144-ball CSP-BGA TGC channel input-referred noise max gain Flexible power-down modes Fast recovery from low power standby mode <2 us Overload recovery <10 ns

Low noise preamplifier LNA Input-referred noise gain = dB Programmable gain dB/17.9 dB/21.3 dB compression 1000 mV p-p/ 750 mV p-p/450 mV p-p Dual-mode active input impedance matching Bandwidth BW >100 MHz

Variable gain amplifier VGA Attenuator range −45 dB to 0 dB Postamp gain PGA 21 dB/24 dB/27 dB/30 dB Linear-in-dB gain control

Antialiasing filter AAF Programmable second-order LPF from 8 MHz to 18 MHz Programmable HPF

Analog-to-digital converter ADC SNR 70 dB, 12 bits up to 80 MSPS Serial LVDS ANSI-644, low power/reduced signal

CW mode I/Q demodulator Individual programmable phase rotation Output dynamic range per channel >160 Output-referred SNR 155 1 kHz offset, −3 dBFS

The AD9279 is designed for low cost, low power, small size, and ease of use for medical ultrasound and automotive radar. It contains eight channels of a variable gain amplifier VGA with a low noise preamplifier LNA , an antialiasing filter AAF , an analog-to-digital converter ADC , and an I/Q demodulator with programmable phase rotation.

Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, and a maximum gain of up to 52 dB. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.

The LNA has a single-ended-to-differential gain that is selectable through the SPI. Assuming a 15 MHz noise bandwidth NBW and a dB LNA gain, the LNA input SNR is roughly 94 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator that has independently programmable phase rotation with 16 phase settings.

Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface.

FUNCTIONAL BLOCK DIAGRAM

AVDD1 AVDD2

PDWN STBY

DRVDD

LO-A TO LO-H

LOSW-A TO LOSW-H LI-A TO LI-H

LG-A TO LG-H

I/Q DEMODULATOR
8 CHANNELS
12-BIT ADC

SERIAL LVDS

DOUTA+ TO DOUTH+ TO

LO GENERATION

REFERENCE

SERIAL PORT INTERFACE

DATA RATE MULTIPLIER

FCO+ DCO+

RESET 4LO+

GAIN+

CWI+ CWQ+ VREF RBIAS GPO[0:3] CSB SCLK SDIO CLK+ 09423-001

Figure

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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2010 Analog Devices, Inc. All rights reserved.

AD9279

TABLE OF CONTENTS

AC 3 Digital Specifications 6 Switching Specifications 7 ADC Timing Diagrams 8 Absolute Maximum 9 Thermal Impedance 9 ESD 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics 13 TGC 13 CW Doppler 16
TGC 20 CW Doppler 33 Serial Port Interface 37 Hardware 37 Memory Map 39 Reading the Memory Map 39 Reserved Locations 39 Default Values 39 Logic 39 Outline Dimensions 43 Ordering Guide 43

AD9279

SPECIFICATIONS

AC SPECIFICATIONS

AVDD1 = V, AVDD2 = V, DRVDD = V, V internal ADC reference, full temperature range −40°C to +85°C , fIN = 5 MHz, RS = 50 Ω, RFB = ∞ unterminated , LNA gain = dB, LNA bias = default, PGA gain = 27 dB, GAIN− = V, GAIN+ = 0 V, AAF LPF cutoff = fSAMPLE/3 MODE I/II = fSAMPLE/4.5 MODE III , HPF cutoff = LPF cutoff/12, MODE I = fSAMPLE = 40 MSPS, MODE II = fSAMPLE = 65 MSPS, MODE III = fSAMPLE = 80 MSPS, low power LVDS mode, unless otherwise noted.

Table

Parameter1

Test Conditions/Comments

LNA CHARACTERISTICS

Gain

Single-ended input to differential
output

Single-ended input to single-ended output
dB Input Compression Point

LNA gain = dB

LNA gain = dB

LNA gain = dB
1 dB Input Compression Point

LNA gain = dB

LNA gain = dB

LNA gain = dB

Input Common Mode LI-x, LG-x

Output Common Mode LO-x

Switch off

Switch on

Output Common Mode LOSW-x Switch off

Switch on

Input Resistance LI-x

RFB = 350 Ω, LNA gain = dB

RFB = 1400 Ω, LNA gain = dB

RFB = ∞, LNA gain = dB

Input Capacitance LI-x
−3 dB Bandwidth

LNA gain = dB

LNA gain = dB

LNA gain = dB

Input Noise Voltage

RS = 0 Ω, RFB = ∞

LNA gain = dB

LNA gain = dB

LNA gain = dB
For optimum performance, the 4LO input is driven differentially, as on the AD9279 evaluation board see the Ordering Guide . The common-mode voltage on each pin is approximately V with the nominal 3 V supply. It is important to ensure that the LO source have very low phase noise jitter , a fast slew rate, and an adequate input level to obtain optimum performance of the CW signal chain.

Beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. A RESET pin is provided to synchronize the LO divider circuits in different AD9279s when they are used in arrays. The RESET pin resets the dividers to a known state after power is applied to multiple AD9279s. Accurate channel-to-channel phase matching can only be achieved via a common pulse on the RESET pin when using more than one AD9279.

AD9279

I/Q Demodulator and Phase Shifter

The I/Q demodulators consist of double-balanced passive mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability matching the LNA output full scale. These currents are then presented to the mixers, which convert them to baseband RF − LO and twice RF + LO . The signals are phase shifted according to the codes programmed into the SPI latch see Table The phase shift function is an integral part of the overall circuit. The phase shift listed in Column 1 of Table 16 is defined as being between the baseband I or Q channel outputs. As an example, for a common signal applied to a pair of RF inputs to an AD9279, the baseband outputs are in phase for matching phase codes. However, if the phase code for Channel 1 is 0000 and that of Channel 2 is 0001, then Channel 2 leads Channel 1 by

Table Phase Select Code for Channel-to-Channel Phase Shift

Shift

I/Q Demodulator Phase SPI Register 0x2D[3:0]
0000
0001
45°
0010
0011
90°
0100
0101
135°
0110
0111
180°
1000
1001
225°
1010
1011
270°
1100
1101
315°
1110
1111

Dynamic Range and Noise

Figure 66 is an interconnection block diagram of all eight channels of the AD9279. Two stages of ADA4841 amplifiers are used. The first stage does an I-to-V conversion and filters the high frequency content that results from the demodulation process. In beamforming applications, the I and Q outputs of a number of receiver channels are summed. In the AD9279, the summation of eight channels is the input to the first stage of the ADA4841s. The second stage of ADA4841 amplifiers is used to do the summation of additional AD9279 to ADA4841 outputs, provide gain, and drive the AD7982, 18-bit SAR ADC. The dynamic range of the system increases by the factor 10log10 N , where N is the total number of channels assuming random uncorrelated noise . The noise in the 8-channel example of Figure 66 is increased by 9 dB while the signal quadruples 18 dB , yielding an aggregate SNR improvement of 18 − 9 = 9 dB.

The output-referred noise of the CW signal path depends on the LNA gain and the selection of the first stage summing amplifier and the value of RFILT. To determine the output referred noise, it is important to know the active low-pass filter LPF values RA, RFILT, and CFILT, shown in Figure Typical filter values for all eight channels of a single AD9279 are 100 Ω for RA, 500 Ω for RFILT, and nF for CFILT these values implement a 100 kHz single-pole LPF.

If the RF and LO are offset by 10 kHz, the demodulated signal is 10 kHz and is passed by the LPF. The single-channel mixing gain from the RF input to the ADA4841 output for example, is approximately the LNA gain for RFILT and CFILT of 500 Ω and nF.

This gain can be increased by increasing the filter resistor while maintaining the corner frequency. The factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the I-to-V converter, in this example, the ADA4841. Because any amplifier has limited drive capability, there is a finite number of channels that can be summed.

CHANNEL A

CHANNEL H

AD9279
4 LO GENERATION

AD9279
ORDERING GUIDE

Model1

Temperature Range

AD9279-BBCZ −40°C to +85°C

AD9279-65EBZ

AD9279-80KITZ
1 Z = RoHS Compliant Part.

Package Description 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] Evaluation Board Evaluation Board and High Speed FPGA-Based Data Capture Board

Package Option BC-144-1

AD9279 NOTES
2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D09423-0-10/10 0
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Datasheet ID: AD9279BBCZ 517771