CY7C1352G-133AXI

CY7C1352G-133AXI Datasheet

CY7C1352G

Part	Datasheet
CY7C1352G-133AXI	CY7C1352G-133AXI (pdf)

Related Parts	Information
CY7C1352G-133AXCT	CY7C1352G-133AXCT

PDF Datasheet Preview
CY7C1352G 4-Mbit 256Kx18 Pipelined SRAM with NoBL Architecture • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 18 common I/O architecture • Single 3.3V power supply • 2.5V / 3.3V I/O Operation • Fast clock-to-output times ns for 250-MHz device ns for 200-MHz device ns for 166-MHz device ns for 133-MHz device • Clock Enable CEN pin to suspend operation • Synchronous self-timed writes • Asynchronous output enable OE • Lead-Free 100 TQFP package • Burst or interleaved burst order • ZZ” Sleep Mode Option and Stop Clock option Functional Description[1] The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 250-MHz device . Write operations are controlled by the two Byte Write Select BW[A:B] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Logic Block Diagram CLK CEN A0, A1, A MODE C ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 ADV/LD BWA BWB WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY A R E G I S T E INPUT REGISTER 1 E INPUT REGISTER 0 E DQs DQPA DQPB OE CE1 CE2 CE3 READ LOGIC Sleep Control Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C1352G Selection Guide 250 MHz Ordering Information Speed MHz Ordering Code Package Name Package Type Operating Range 250 CY7C1352G-250AXC A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial CY7C1352G-250AXI A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial 200 CY7C1352G-200AXC A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial CY7C1352G-200AXI A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial 166 CY7C1352G-166AXC A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial CY7C1352G-166AXI A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial 133 CY7C1352G-133AXC A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial CY7C1352G-133AXI A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial Shaded areas contain advance information. Please contact your local cypress sales representative to order parts that are not listed in the ordering information table. Package Diagram 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 51-85050-A 51-85050-A ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Page 12 of 13 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1352G Document History Page Document Title CY7C1352G 4-Mbit 256Kx18 Pipelined SRAM with NoBL Architecture Document Number 38-05514 Orig. of ECN NO. Issue Date Change Description of Change 224362 See ECN RKF New data sheet 288431 See ECN VBL Deleted 100 MHz and 225 MHz Changed TQFP package in Ordering Information section to lead-free TQFP 332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal Resistance table Added lead-free product information for 119 BGA Updated the Ordering Information by shading and unshading MPN’s as per availability Page 13 of 13

PDF Datasheet Preview

CY7C1352G
4-Mbit 256Kx18 Pipelined SRAM with NoBL Architecture
• Pin compatible and functionally equivalent to ZBT devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• 2.5V / 3.3V I/O Operation
• Fast clock-to-output times
ns for 250-MHz device ns for 200-MHz device ns for 166-MHz device ns for 133-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable OE
• Lead-Free 100 TQFP package
• Burst or interleaved burst order
• ZZ” Sleep Mode Option and Stop Clock option

Functional Description[1]

The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 250-MHz device .

Write operations are controlled by the two Byte Write Select BW[A:B] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Logic Block Diagram

CLK CEN

A0, A1, A

MODE C

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

ADV/LD BWA BWB

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

WRITE DRIVERS

MEMORY

ARRAY A

R E G I S T E

INPUT REGISTER 1 E

INPUT REGISTER 0 E

DQs DQPA DQPB

OE CE1 CE2 CE3

READ LOGIC

Sleep Control

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C1352G

Selection Guide
250 MHz
Ordering Information

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
250 CY7C1352G-250AXC

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial

CY7C1352G-250AXI

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm

Industrial
200 CY7C1352G-200AXC

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial

CY7C1352G-200AXI

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm

Industrial
166 CY7C1352G-166AXC

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial

CY7C1352G-166AXI

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm

Industrial
133 CY7C1352G-133AXC

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial

CY7C1352G-133AXI

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm

Industrial
Shaded areas contain advance information. Please contact your local cypress sales representative to order parts that are not listed in the ordering information table.

Package Diagram
100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101
51-85050-*A 51-85050-*A

ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.

Page 12 of 13

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C1352G

Document History Page

Document Title CY7C1352G 4-Mbit 256Kx18 Pipelined SRAM with NoBL Architecture Document Number 38-05514

Orig. of ECN NO. Issue Date Change

Description of Change
224362 See ECN

RKF New data sheet
288431 See ECN

VBL Deleted 100 MHz and 225 MHz
Changed TQFP package in Ordering Information section to lead-free TQFP
332895 See ECN

SYT Modified Address Expansion balls in the pinouts for 100 TQFP Package as
per JEDEC standards and updated the Pin Definitions accordingly

Modified VOL, VOH test conditions Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal Resistance table

Added lead-free product information for 119 BGA
Updated the Ordering Information by shading and unshading MPN’s as per
availability

Page 13 of 13

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1352G-133AXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1352G-133AXI 507980