CY7C1334H-166AXC

CY7C1334H-166AXC Datasheet

CY7C1334H

Part	Datasheet
CY7C1334H-166AXC	CY7C1334H-166AXC (pdf)

PDF Datasheet Preview
CY7C1334H 2-Mbit 64K x 32 Pipelined SRAM with NoBL Architecture Functional Description[1] • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 64K x 32 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times ns for 166-MHz device ns for 133-MHz device • Clock Enable CEN pin to suspend operation • Synchronous self-timed write • Asynchronous output enable OE • Offered in Lead-Free JEDEC-standard 100-pin TQFP package • Burst or interleaved burst order • “ZZ” Sleep mode option Logic Block Diagram The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 166-MHz device Write operations are controlled by the four Byte Write Select BW[A:D] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. CLK CEN A0, A1, A MODE C ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 ADV/LD BWA BWB BWC BWD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY O U T P U T R E G I S T E R S E D A T A S T E R I N O U T P U T B U F E R S E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 READ LOGIC SLEEP CONTROL Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 166 CY7C1334H-166AXC Package Diagram Package Diagram Package Type 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Operating Range Commercial 100-pin TQFP 14 x 20 x mm 51-85050 51-85050-C NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders. Page 12 of 13 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1334H Document History Page Document Title CY7C1334H 2-Mbit 64K x 32 Pipelined SRAM with NoBL Architecture Document Number 38-05678 Orig. of ECN NO. Issue Date Change Description of Change 347357 See ECN PCI New Data Sheet 424820 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-State to Tri-State. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Modified test condition from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table. Replaced Package Diagram of 51-85050 from A to *B 459347 See ECN NXR Converted from Preliminary to Final Included 2.5V I/O option Updated the Ordering Information table. 2896585 03/20/2010 NJY Removed obsolete part numbers from Ordering Information table and updated package diagrams. Page 13 of 13 [+] Feedback

PDF Datasheet Preview

CY7C1334H
2-Mbit 64K x 32 Pipelined SRAM with NoBL Architecture

Functional Description[1]
• Pin compatible and functionally equivalent to ZBT devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte Write capability
• 64K x 32 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
ns for 166-MHz device ns for 133-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed write
• Asynchronous output enable OE
• Offered in Lead-Free JEDEC-standard 100-pin TQFP package
• Burst or interleaved burst order
• “ZZ” Sleep mode option

Logic Block Diagram

The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 166-MHz device

Write operations are controlled by the four Byte Write Select BW[A:D] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

CLK CEN

A0, A1, A

MODE C

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

ADV/LD

BWA BWB BWC BWD

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

WRITE DRIVERS

MEMORY

ARRAY

O U T P U T R E G I S T E R S E

D A T A S T E R I N

O U T P U T

B U F E R S E

INPUT REGISTER 1 E

INPUT REGISTER 0 E

OE CE1 CE2 CE3

READ LOGIC

SLEEP CONTROL

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
166 CY7C1334H-166AXC

Package Diagram

Package Diagram

Package Type
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Operating Range

Commercial
100-pin TQFP 14 x 20 x mm 51-85050
51-85050-*C

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 12 of 13

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY7C1334H

Document History Page

Document Title CY7C1334H 2-Mbit 64K x 32 Pipelined SRAM with NoBL Architecture Document Number 38-05678

Orig. of ECN NO. Issue Date Change

Description of Change
347357 See ECN

PCI New Data Sheet
424820 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Changed Three-State to Tri-State.

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table.
Modified test condition from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering

Information table.

Replaced Package Diagram of 51-85050 from *A to *B
459347 See ECN NXR Converted from Preliminary to Final

Included 2.5V I/O option
Updated the Ordering Information table.
2896585 03/20/2010 NJY Removed obsolete part numbers from Ordering Information table and
updated package diagrams.

Page 13 of 13 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1334H-166AXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1334H-166AXC 507968