CY7C1324H-133AXC

CY7C1324H-133AXC Datasheet

CY7C1324H

Part	Datasheet
CY7C1324H-133AXC	CY7C1324H-133AXC (pdf)

Related Parts	Information
CY7C1324H-133AXCT	CY7C1324H-133AXCT

PDF Datasheet Preview
CY7C1324H 2-Mbit 128 K x 18 Flow-Through Sync SRAM 2-Mbit 128 K x 18 flow-through Sync SRAM • 128 K x 18 common I/O • V core power supply • / 2.5-V I/O supply • Fast clock-to-output times ns 133 MHz version • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Offered in JEDEC-standard Pb-free 100-pin thin quad flat pack TQFP package • “ZZ” sleep mode option Selection Guide Maximum access time Maximum operating current Maximum standby current 133 MHz 225 40 Functional Description The CY7C1324H[1] is a 128 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133 MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BW[A:B], and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. The CY7C1324H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . The CY7C1324H operates from a V core power supply while all outputs may operate with either a V or V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Unit Note Refer to the application note, SRAM System Design Guidelines for more information on best-practices recommendations. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram A0,A1,A MODE ADV CLK ADSC ADSP ADDRESS REGISTER A[1:0] BURST Q1 COUNTER AND LOGIC DQB,DQPB WRITE REGISTER BWA BWE GW CE1 CE2 CE3 DQA,DQPA WRITE REGISTER ENABLE REGISTER SLEEP CONTROL CY7C1324H DQB,DQPB WRITE DRIVER DQA,DQPA WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs DQPA DQPB INPUT REGISTERS Page 2 of 19 [+] Feedback CY7C1324H Contents Maximum Ratings 9 Operating Range 9 Electrical Characteristics 9 Capacitance 10 Thermal Resistance 10 Switching Characteristics 11 Timing Diagrams 12 Ordering Information 16 Ordering Code Definitions 16 Package Diagram 16 Acronyms 17 Document Conventions 17 Units of Measure 17 Document History Page 18 Sales, Solutions, and Legal Information 19 Worldwide Sales and Design Support 19 Products 19 PSoC Solutions 19 Page 3 of 19 [+] Feedback Pin Configurations Figure 100-Pin TQFP Pinout[2] CY7C1324H 100 A 99 A 98 CE1 97 CE2 96 NC 95 NC 94 BWB 93 BWA 92 CE3 91 VDD 90 VSS 89 CLK 88 GW 87 BWE 86 OE 85 ADSC 84 ADSP 83 ADV 82 A 81 A BYTE B VDDQ VDDQ VDDQ DQPB VDDQ CY7C1324H VDDQ DQPB VDDQ VDDQ VDDQ BYTE A NC/9M 43 NC/18M 42 NC/36M 39 NC/72M 38 NC/4M MODE Note Refer to the application note, AN4025 for more information on SRAM address and I/O pin order. Page 4 of 19 [+] Feedback CY7C1324H Pin Definitions Name A0, A1, A BWA,BWB GW BWE CLK CE1 CE2 CE3 OE ADV ADSP ADSC ZZ DQs DQPA, DQPB VDD VSS InputSynchronous InputSynchronous Address Inputs used to select one of the 128 K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled on the rising edge of CLK. InputSynchronous Ordering Information Table 1 lists the CY7C1324H key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Table Key Features and Ordering Information Speed MHz Ordering Code Package Diagram Package Type 133 CY7C1324H-133AXC 51-85050 100-pin TQFP 14 x 20 x mm Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 13XX H XXX A X,C Package Type A = TQFP, X = Pb-free Temperature Grade C = Commercial Maximum operating frequency 90 nm 2-Mbit 128 K x 18 Flow-Through Sync SRAM Technology CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Package Diagram 51-85050 C Page 16 of 19 [+] Feedback Acronyms Table Acronyms Used in this Document Acronym I/O JEDEC TQFP Description input/output joint electron device engineering council thin quad flat pack Document Conventions Units of Measure Table Units of Measure Unit of Measure degree Celsius megahertz micro amperes milliamperes millimeters nano seconds ohms percent pico Farad volts watts CY7C1324H Page 17 of 19 [+] Feedback CY7C1324H Document History Page Document Title CY7C1324H 2-Mbit 128 K x 18 Flow-Through Sync SRAM Document Number 001-00208 Orig. of Submission Change Description of Change 347377 See ECN New datasheet 428408 See ECN Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from Modified test condition from VIH < VDD to VIH VDD Replaced Package Name column with Package Diagram in the Ordering Infor- mation table. Updated the Ordering Information Table. Replaced Package Diagram of 51-85050 from A to *B 459347 See ECN Included V I/O option Updated the Ordering Information table. 2897120 03/22/10 Removed inactive parts from Ordering Information table Updated package diagram. 3025128 RAJA/NJY 09/08/10 Template update. Added ordering code definitions, acronyms, units of measure, reference documents, and table of contents. Page 18 of 19 [+] Feedback CY7C1324H Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. PSoC Designer is a trademark and are registered trademarks of Cypress Semiconductor Corporation. Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 19 of 19 [+] Feedback

PDF Datasheet Preview

CY7C1324H
2-Mbit 128 K x 18 Flow-Through Sync SRAM
2-Mbit 128 K x 18 flow-through Sync SRAM
• 128 K x 18 common I/O
• V core power supply
• / 2.5-V I/O supply
• Fast clock-to-output times
ns 133 MHz version
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard Pb-free 100-pin thin quad flat
pack TQFP package
• “ZZ” sleep mode option

Selection Guide

Maximum access time Maximum operating current Maximum standby current
133 MHz 225 40

Functional Description

The CY7C1324H[1] is a 128 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133 MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BW[A:B], and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. The CY7C1324H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

The CY7C1324H operates from a V core power supply while all outputs may operate with either a V or V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Unit

Note Refer to the application note, SRAM System Design Guidelines for more information on best-practices recommendations.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram

A0,A1,A MODE ADV CLK

ADSC ADSP

ADDRESS REGISTER

A[1:0]

BURST Q1 COUNTER AND

LOGIC

DQB,DQPB WRITE REGISTER

BWA BWE GW CE1 CE2 CE3

DQA,DQPA WRITE REGISTER

ENABLE REGISTER

SLEEP

CONTROL

CY7C1324H

DQB,DQPB WRITE DRIVER

DQA,DQPA WRITE DRIVER

MEMORY ARRAY

SENSE AMPS

OUTPUT BUFFERS

DQs DQPA DQPB

INPUT REGISTERS

Page 2 of 19 [+] Feedback

CY7C1324H

Contents
Maximum Ratings 9 Operating Range 9 Electrical Characteristics 9 Capacitance 10 Thermal Resistance 10 Switching Characteristics 11 Timing Diagrams 12 Ordering Information 16
Ordering Code Definitions 16 Package Diagram 16 Acronyms 17 Document Conventions 17

Units of Measure 17 Document History Page 18 Sales, Solutions, and Legal Information 19

Worldwide Sales and Design Support 19 Products 19 PSoC Solutions 19

Page 3 of 19 [+] Feedback

Pin Configurations

Figure 100-Pin TQFP Pinout[2]

CY7C1324H
100 A 99 A 98 CE1 97 CE2 96 NC 95 NC 94 BWB 93 BWA 92 CE3 91 VDD 90 VSS 89 CLK 88 GW 87 BWE 86 OE 85 ADSC 84 ADSP 83 ADV 82 A 81 A

BYTE B

VDDQ

VDDQ

VDDQ

DQPB

VDDQ

CY7C1324H

VDDQ

DQPB

VDDQ

VDDQ

VDDQ

BYTE A

NC/9M 43

NC/18M 42

NC/36M 39

NC/72M 38

NC/4M

MODE

Note Refer to the application note, AN4025 for more information on SRAM address and I/O pin order.

Page 4 of 19 [+] Feedback

CY7C1324H

Pin Definitions

Name A0, A1, A BWA,BWB GW BWE CLK CE1 CE2 CE3 OE

ADV ADSP

ADSC

ZZ DQs DQPA, DQPB

VDD VSS

InputSynchronous

InputSynchronous

Address Inputs used to select one of the 128 K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled on the rising edge of CLK.

InputSynchronous
Ordering Information
Table 1 lists the CY7C1324H key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at
Table Key Features and Ordering Information

Speed MHz
Ordering Code

Package Diagram

Package Type
133 CY7C1324H-133AXC 51-85050 100-pin TQFP 14 x 20 x mm Pb-free

Operating Range

Commercial
Ordering Code Definitions

CY 7 C 13XX H XXX A X,C Package Type A = TQFP, X = Pb-free Temperature Grade C = Commercial

Maximum operating frequency
90 nm
2-Mbit 128 K x 18 Flow-Through Sync SRAM

Technology CMOS Marketing Code 7 = SRAM Company ID CY = Cypress

Package Diagram
51-85050 *C

Page 16 of 19 [+] Feedback

Acronyms

Table Acronyms Used in this Document

Acronym I/O JEDEC TQFP

Description input/output joint electron device engineering council thin quad flat pack

Document Conventions

Units of Measure

Table Units of Measure

Unit of Measure
degree Celsius
megahertz
micro amperes
milliamperes
millimeters
nano seconds
ohms
percent
pico Farad
volts
watts

CY7C1324H

Page 17 of 19 [+] Feedback

CY7C1324H

Document History Page

Document Title CY7C1324H 2-Mbit 128 K x 18 Flow-Through Sync SRAM Document Number 001-00208

Orig. of Submission

Change

Description of Change
347377

See ECN New datasheet
428408

See ECN Converted from Preliminary to Final.

Changed address of Cypress Semiconductor Corporation on Page# 1 from
Modified test condition from VIH < VDD to VIH VDD Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table.
Updated the Ordering Information Table.

Replaced Package Diagram of 51-85050 from *A to *B
459347

See ECN Included V I/O option
Updated the Ordering Information table.
2897120
03/22/10 Removed inactive parts from Ordering Information table Updated package
diagram.
3025128 RAJA/NJY 09/08/10 Template update.
Added ordering code definitions, acronyms, units of measure, reference
documents, and table of contents.

Page 18 of 19 [+] Feedback

CY7C1324H

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

PSoC Designer is a trademark and are registered trademarks of Cypress Semiconductor Corporation. Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 19 of 19 [+] Feedback

More datasheets: WS1403-BLK | 94779 | 94783 | 94769 | 94775 | 94773 | 94777 | 94771 | 94781 | 94767

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Datasheet ID: CY7C1324H-133AXC 507964