CY7C1318BV18-250BZC

CY7C1318BV18-250BZC Datasheet

 CY7C1318BV18, CY7C1320BV18

Part	Datasheet
CY7C1318BV18-250BZC	CY7C1318BV18-250BZC (pdf)

Related Parts	Information
CY7C1318BV18-167BZC	CY7C1318BV18-167BZC

PDF Datasheet Preview
 CY7C1318BV18, CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double Data Rate DDR interfaces  data transferred at 600 MHz at 300 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage • Available in 165-Ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations CY7C1316BV18 2M x 8 CY7C1916BV18 2M x 9 CY7C1318BV18 1M x 18 CY7C1320BV18 512K x 36 Functional Description The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1316BV18 and two 9-bit words in the case of CY7C1916BV18 that burst sequentially into or out of the device. The burst counter always starts with a ‘0’ internally in the case of CY7C1316BV18 and CY7C1916BV18. For CY7C1318BV18 and CY7C1320BV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1318BV18 of two 36-bit words in the case of CY7C1320BV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs, D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 278 MHz 278 775 780 805 855 250 MHz 250 705 710 730 775 200 MHz 200 575 580 600 635 167 MHz 167 490 510 540 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1316BV18 CY7C1318BV18, CY7C1320BV18 A 19:0 K DOFF VREF R/W NWS[1:0] Address Register CLK Gen. Control Logic Write Add. Decode Read Add. Decode Write Reg Write Reg 1M x 8 Array 1M x 8 Array Read Data Reg. 16 8 Output Logic Control Reg. Reg. 8 Reg. CQ DQ[7:0] Logic Block Diagram CY7C1916BV18 Power Up Sequence 19 DLL Constraints 19 Maximum Ratings 20 Operating Range 20 Electrical Characteristics 20 DC Electrical Characteristics 20 AC Electrical Characteristics 21 Capacitance 22 Thermal Resistance 22 Switching Characteristics 23 Switching Waveforms 25 Ordering Information 26 Package Diagram 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29 Page 4 of 30 [+] Feedback CY7C1318BV18, CY7C1320BV18 Pin Configuration The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow. [1] 165-Ball FBGA 13 x 15 x mm Pinout CY7C1316BV18 2M x 8 CQ NC/72M NWS1 K NC/144M LD NC/36M A NC/288M K NWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 11 CQ DQ3 NC DQ2 NC ZQ NC DQ0 NC TDI CY7C1916BV18 2M x 9 CQ NC/72M K NC/144M LD NC/36M CQ A NC/288M K BWS0 VDDQ VDDQ Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 250 CY7C1318BV18-250BZC CY7C1320BV18-250BZI 200 CY7C1320BV18-200BZC 167 CY7C1318BV18-167BZC CY7C1320BV18-167BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Operating Range Commercial Industrial Commercial Ordering Code Definition CY 7 C 13XX B V18 - XXX BZ X, C, I Package Type  BZ = FBGA, X = Pb-free, C = Commercial, I = Industrial Maximum operating frequency Voltage V 90 nm 18-Mbit DDR II SRAM 2-word burst architecture Technology CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Page 27 of 30 [+] Feedback CY7C1318BV18, CY7C1320BV18 Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 51-85180 C Page 28 of 30 [+] Feedback CY7C1318BV18, CY7C1320BV18 Document History Page Document Title CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Architecture Document Number 38-05621 ECN No. Submission Date Orig, of Change Description of Change * 252474 See ECN New data sheet A 325581 See ECN Removed CY7C1320BV18 from the title Included 300-MHz Speed Bin Added Industrial Temperature Grade Replaced TBDs for IDD and ISB1 specs Replaced the TBDs on the Thermal Characteristics Table to = 28.51C/W and = 5.91C/W Replaced TBDs in the Capacitance Table for the 165 FBGA Package Changed the package diagram from BB165E 15 x 17 x mm to BB165D 13 x 15 x mm Added Lead-Free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per avail- ability B 413997 See ECN Converted from Preliminary to Final Added CY7C1916BV18 part number to the title Added 278-MHz speed Bin Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed C/C Pin Description in the features section and Pin Description Added power-up sequence details and waveforms Added foot notes #15, 16, 17 on page# 19 Replaced Three-state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 20 Modified the IDD and ISB values Modified test condition in Footnote #18 on page# 20 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table C 472384 See ECN Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from C to +85 C to C to +125 C Added additional notes in the AC parameter section Modified AC Switching Waveform Corrected the typo In the AC Switching Characteristics Table Updated the Ordering Information Table Page 29 of 30 [+] Feedback CY7C1318BV18, CY7C1320BV18 Document History Page Document Title CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Architecture Document Number 38-05621 D 2511674 06/03/08 VKN/PYRS Updated Logic Block diagrams Updated IDD/ISB specs Added footnote# 19 related to IDD Updated power up sequence waveform and its description Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed spec from to Changed spec from to Changed tCYC maximum spec to ns for all speed bins Modified footnotes 21 and 28 E 2896585 03/21/2010 Removed obsolete parts. Updated package diagram, data sheet template, and Sales, Solutions, and Legal Information section. F 3068494 10/21/2010 HMLA Removed inactive part - CY7C1318BV18-278BZC in Ordering Information table. Added Ordering Code Definition. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 30 of 30 DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

 CY7C1318BV18, CY7C1320BV18
18-Mbit DDR-II SRAM 2-Word Burst Architecture
• 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36
• 300 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double Data Rate DDR interfaces 
data transferred at 600 MHz at 300 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high-speed
systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage
• Available in 165-Ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

CY7C1316BV18 2M x 8 CY7C1916BV18 2M x 9 CY7C1318BV18 1M x 18 CY7C1320BV18 512K x 36

Functional Description

The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1316BV18 and two 9-bit words in the case of CY7C1916BV18 that burst sequentially into or out of the device. The burst counter always starts with a ‘0’ internally in the case of CY7C1316BV18 and CY7C1916BV18. For CY7C1318BV18 and CY7C1320BV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1318BV18 of two 36-bit words in the case of CY7C1320BV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs, D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
300 MHz
278 MHz 278 775 780 805 855
250 MHz 250 705 710 730 775
200 MHz 200 575 580 600 635
167 MHz 167 490 510 540

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1316BV18

CY7C1318BV18, CY7C1320BV18

A 19:0

K DOFF

VREF R/W NWS[1:0]

Address Register

CLK Gen.

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg
1M x 8 Array 1M x 8 Array

Read Data Reg. 16 8

Output Logic

Control

Reg.

Reg. 8

Reg.

CQ DQ[7:0]

Logic Block Diagram CY7C1916BV18
Power Up Sequence 19 DLL Constraints 19 Maximum Ratings 20 Operating Range 20 Electrical Characteristics 20 DC Electrical Characteristics 20 AC Electrical Characteristics 21 Capacitance 22 Thermal Resistance 22 Switching Characteristics 23 Switching Waveforms 25 Ordering Information 26 Package Diagram 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29

Page 4 of 30 [+] Feedback

CY7C1318BV18, CY7C1320BV18

Pin Configuration

The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow. [1]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C1316BV18 2M x 8

CQ NC/72M

NWS1

K NC/144M LD

NC/36M

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
11 CQ DQ3 NC DQ2 NC ZQ NC DQ0 NC TDI

CY7C1916BV18 2M x 9

CQ NC/72M

K NC/144M LD

NC/36M CQ

A NC/288M K

BWS0

VDDQ

VDDQ
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
250 CY7C1318BV18-250BZC

CY7C1320BV18-250BZI
200 CY7C1320BV18-200BZC
167 CY7C1318BV18-167BZC

CY7C1320BV18-167BZC

Package Diagram

Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial Industrial

Commercial
Ordering Code Definition

CY 7 C
13XX

B V18 - XXX BZ X, C, I

Package Type  BZ = FBGA, X = Pb-free, C = Commercial, I = Industrial

Maximum operating frequency

Voltage V
90 nm 18-Mbit DDR II SRAM 2-word burst architecture

Technology CMOS Marketing Code 7 = SRAM

Company ID CY = Cypress

Page 27 of 30 [+] Feedback

CY7C1318BV18, CY7C1320BV18

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180
51-85180 *C

Page 28 of 30 [+] Feedback

CY7C1318BV18, CY7C1320BV18

Document History Page

Document Title CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Architecture Document Number 38-05621

ECN No.

Submission Date

Orig, of Change

Description of Change
** 252474 See ECN

New data sheet
*A 325581 See ECN

Removed CY7C1320BV18 from the title

Included 300-MHz Speed Bin

Added Industrial Temperature Grade

Replaced TBDs for IDD and ISB1 specs Replaced the TBDs on the Thermal Characteristics Table to = 28.51C/W and = 5.91C/W Replaced TBDs in the Capacitance Table for the 165 FBGA Package

Changed the package diagram from BB165E 15 x 17 x mm to BB165D
13 x 15 x mm

Added Lead-Free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per avail-
ability
*B 413997 See ECN
Converted from Preliminary to Final Added CY7C1916BV18 part number to the title Added 278-MHz speed Bin Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed C/C Pin Description in the features section and Pin Description Added power-up sequence details and waveforms Added foot notes #15, 16, 17 on page# 19 Replaced Three-state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 20 Modified the IDD and ISB values Modified test condition in Footnote #18 on page# 20 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table
*C 472384 See ECN
Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from C to +85 C to C to +125 C Added additional notes in the AC parameter section Modified AC Switching Waveform Corrected the typo In the AC Switching Characteristics Table Updated the Ordering Information Table

Page 29 of 30 [+] Feedback

CY7C1318BV18, CY7C1320BV18

Document History Page

Document Title CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Architecture Document Number 38-05621
*D 2511674 06/03/08

VKN/PYRS

Updated Logic Block diagrams Updated IDD/ISB specs Added footnote# 19 related to IDD Updated power up sequence waveform and its description Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed spec from to Changed spec from to Changed tCYC maximum spec to ns for all speed bins Modified footnotes 21 and 28
*E 2896585 03/21/2010

Removed obsolete parts. Updated package diagram, data sheet template, and

Sales, Solutions, and Legal Information section.
*F 3068494 10/21/2010

HMLA
Removed inactive part - CY7C1318BV18-278BZC in Ordering Information table. Added Ordering Code Definition.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 30 of 30

DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1318BV18-250BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1318BV18-250BZC 507959