CY7C1314JV18-250BZXC

CY7C1314JV18-250BZXC Datasheet

CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18

Part	Datasheet
CY7C1314JV18-250BZXC	CY7C1314JV18-250BZXC (pdf)

PDF Datasheet Preview
CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture • Separate independent read and write data ports Supports concurrent transactions • 250 MHz clock for high bandwidth • 2-word burst on all accesses • Double Data Rate DDR interfaces on both read and write ports data transferred at 500 MHz at 250 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high speed systems • Single multiplexed address input bus latches address inputs for both read and write ports • Separate port selects for depth expansion • Synchronous internally self-timed writes • QDR -II operates with cycle read latency when Delay Lock Loop DLL is enabled • Operates similar to a QDR-I device with 1 cycle read latency in DLL off mode • Available in x 8, x 9, x 18, and x 36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD • Available in 165-Ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • Variable drive HSTL output buffers • JTAG compatible test access port • DLL for accurate data placement Configurations CY7C1310JV18 2M x 8 CY7C1910JV18 2M x 9 CY7C1312JV18 1M x 18 CY7C1314JV18 512K x 36 Functional Description The CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, and CY7C1314JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 8-bit words CY7C1310JV18 , 9-bit words CY7C1910JV18 , 18-bit words CY7C1312JV18 , or 36-bit words CY7C1314JV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 250 MHz Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1310JV18 CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 D[7:0] A 19:0 20 Address Register K DOFF VREF WPS NWS[1:0] CLK Gen. Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1310JV18-250BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1910JV18-250BZC CY7C1312JV18-250BZC CY7C1314JV18-250BZC CY7C1310JV18-250BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1910JV18-250BZXC CY7C1312JV18-250BZXC CY7C1314JV18-250BZXC CY7C1310JV18-250BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1910JV18-250BZI CY7C1312JV18-250BZI CY7C1314JV18-250BZI CY7C1310JV18-250BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1910JV18-250BZXI CY7C1312JV18-250BZXI CY7C1314JV18-250BZXI Page 24 of 26 [+] Feedback CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B - 01.0665X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X

PDF Datasheet Preview

CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18
18 Mbit QDR -II SRAM 2-Word Burst Architecture
• Separate independent read and write data ports Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 2-word burst on all accesses
• Double Data Rate DDR interfaces on both read and write ports data transferred at 500 MHz at 250 MHz
• Two input clocks K and K for precise DDR timing SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• QDR -II operates with cycle read latency when Delay Lock Loop DLL is enabled
• Operates similar to a QDR-I device with 1 cycle read latency in DLL off mode
• Available in x 8, x 9, x 18, and x 36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• Variable drive HSTL output buffers
• JTAG compatible test access port
• DLL for accurate data placement

Configurations

CY7C1310JV18 2M x 8 CY7C1910JV18 2M x 9 CY7C1312JV18 1M x 18 CY7C1314JV18 512K x 36

Functional Description

The CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, and CY7C1314JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 8-bit words CY7C1310JV18 , 9-bit words CY7C1910JV18 , 18-bit words CY7C1312JV18 , or 36-bit words CY7C1314JV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
250 MHz

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1310JV18

CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18

D[7:0]

A 19:0 20

Address Register

K DOFF

VREF WPS NWS[1:0]

CLK Gen.
Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1310JV18-250BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1910JV18-250BZC

CY7C1312JV18-250BZC

CY7C1314JV18-250BZC

CY7C1310JV18-250BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1910JV18-250BZXC

CY7C1312JV18-250BZXC

CY7C1314JV18-250BZXC

CY7C1310JV18-250BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1910JV18-250BZI

CY7C1312JV18-250BZI

CY7C1314JV18-250BZI

CY7C1310JV18-250BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1910JV18-250BZXI

CY7C1312JV18-250BZXI

CY7C1314JV18-250BZXI

Page 24 of 26 [+] Feedback

CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B - 01.0665X
11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M N P R
0.15 4X

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Datasheet ID: CY7C1314JV18-250BZXC 507951