LH28F160S5HT-L70

LH28F160S5HT-L70 Datasheet

LH28F160S5HT-L70

Part	Datasheet
LH28F160S5HT-L70	LH28F160S5HT-L70 (pdf)

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PRODUCT SPECIFICATIONS Integrated Circuits Group LH28F160S5HT-L70 Flash Memory 16M 2MB x 8 / 1MB x 16 Model No. LHF16KA3 Spec No. EL127109B Issue Date March 21, 2001 LHF16KA3 ●Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. 1 The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph 2 , even for the following application areas, be sure to observe the precautions given in Paragraph Never use the products for the equipment listed in Paragraph •Office electronics •Instrumentation and measuring equipment •Machine tools •Audiovisual equipment •Home appliance •Communication equipment other than for trunk lines 2 Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. •Control and safety devices for airplanes, trains, automobiles, and other transportation equipment •Mainframe computers •Traffic control systems •Gas leak detectors and automatic cutoff devices •Rescue and security equipment •Other safety devices and safety equipment, etc. 3 Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. •Aerospace equipment •Communications equipment for trunk lines •Control equipment for the nuclear power industry •Medical equipment related to life support, etc. 4 Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. ●Please direct all queries regarding the products covered herein to a sales representative of the company. LHF16KA3 CONTENTS 1 INTRODUCTION 3 Product 3 2 PRINCIPLES OF OPERATION 6 Data Protection 7 3 BUS 7 Read 7 Output Disable 7 Deep Power-Down 7 Read Identifier Codes Operation 8 Query 8 4 COMMAND DEFINITIONS 8 Read Array 11 Read Identifier Codes Command 11 Read Status Register Command....................... 11 Clear Status Register Command....................... 11 Query 12 Block Status Register 12 CFI Query Identification String..................... 13 System Interface Information....................... 13 Device Geometry Definition 14 SCS OEM Specific Extended Query Table 14 Block Erase 15 Full Chip Erase Command 15 Word/Byte Write Command............................... 16 Multi Word/Byte Write Command 16 Block Erase Suspend Command..................... 17 Multi Word/Byte Write Suspend Command... 17 Set Block Lock-Bit Command.......................... 18 Clear Block Lock-Bits Command..................... 18 STS Configuration Command 19 5 DESIGN CONSIDERATIONS Three-Line Output Control STS and Block Erase, Full Chip Erase, Multi Word/Byte Write and Block Lock-Bit Configuration Power Supply Decoupling VPP Trace on Printed Circuit Boards VCC, VPP, RP# Power-Up/Down Power Dissipation 6 ELECTRICAL Absolute Maximum Ratings Operating Conditions Capacitance AC Input/Output Test Conditions..................33 DC AC Characteristics - Read-Only Operations AC Characteristics - Write Operations..........39 Alternative CE#-Controlled Writes Reset Operations Block Erase, Full Chip Erase, Multi Word/Byte Write and Block Lock-Bit Configuration Performance...........................44 7 ADDITIONAL INFORMATION Ordering Information 8 PACKAGE AND PACKING SPECIFICATION........46 LHF16KA3 LH28F160S5HT-L70 16M-BIT 2MBx8/1MBx16 Smart 5 Flash MEMORY • Smart 5 Technology 5V VCC 5V VPP • Common Flash Interface CFI Universal & Upgradable Interface • Scalable Command Set SCS • High Speed Write Performance 32 Bytes x 2 plane Page Buffer 2µs/Byte Write Transfer Rate • High Speed Read Performance 70ns 5V±0.25V , 90ns 5V±0.5V • Operating Temperature -40°C to +85°C • Enhanced Automated Suspend Options Write Suspend to Read Block Erase Suspend to Write Block Erase Suspend to Read • High-Density Symmetrically-Blocked Architecture Thirty-two 64K-byte Erasable Blocks • SRAM-Compatible Write Interface • User-Configurable x8 or x16 Operation • Enhanced Data Protection Features Absolute Protection with VPP=GND Flexible Block Locking Erase/Write Lockout during Power Transitions • Extended Cycling Capability 100,000 Block Erase Cycles Million Block Erase Cycles/Chip • Low Power Management Deep Power-Down Mode Automatic Power Savings Mode Decreases ICC in Static Mode • Automated Write and Erase Command User Interface Status Register • Industry-Standard Packaging 56-Lead TSOP • ETOXTM* V Nonvolatile Flash Technology • CMOS Process P-type silicon substrate • Not designed or rated as radiation hardened SHARP’s LH28F160S5HT-L70 Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S5HT-L70 offers three levels of protection absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F160S5HT-L70 is conformed to the flash Scalable Command Set SCS and the Common Flash Interface CFI specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. The LH28F160S5HT-L70 is manufactured on SHARP’s 0.35µm ETOXTM* V process technology. It come in industry-standard package the 56-Lead TSOP, ideal for board constrained applications. ETOX is a trademark of Intel Corporation. LHF16KA3 1 INTRODUCTION This datasheet contains LH28F160S5HT-L70 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. Product Overview The LH28F160S5HT-L70 is a high-performance 16Mbit Smart 5 Flash memory organized as 2MBx8/1MBx16. The 2MB of data is arranged in thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure Smart 5 technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 5V VCC provides the highest read performance. VPP at 5V eliminates the need for a separate 12V converter, while VPP=5V maximizes erase and write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when Table VCC and VPP Voltage Combinations Offered by Smart 5 Technology VCC Voltage 5V VPP Voltage 5V Internal VCC and VPP detection Circuitry automatically configures the device for optimized read and write operations. A Command User Interface CUI serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine WSM automatically executes the algorithms and timings necessary for block erase, full chip erase, multi word/byte write and block lock-bit configuration operations. A block erase operation erases one of the device’s 64K-byte blocks typically within 0.34s 5V VCC, 5V VPP independent of other blocks. Each block can be independently erased 100,000 times million block erases per device . Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. A word/byte write is performed in byte increments typically within 9.24µs 5V VCC, 5V VPP . A multi word/byte write has high speed write performance of 2µs/byte 5V VCC, 5V VPP . Multi Word/byte write suspend mode enables the system to read data or See Ordering Information for device speeds valid operational combinations . See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit High Speed Configuration for testing characteristics. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit Standard Configuration for testing characteristics. LHF16KA3 ADDRESSES A VIH CE# E VIH OE# G VIH WE# W VOH DATA D/Q Standby HIGH Z Device Address Selection Address Stable Data Valid tAVAV tELQV tGLQX tELQX tGLQV tAVQV Valid Output tEHQZ tGHQZ tOH HIGH Z VIH RP# P tPHQV NOTE CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High. Figure AC Waveform for Read Operations LHF16KA3 ADDRESSES A VIH CE# E VIH OE# G Standby Device Address Selection Address Stable Data Valid tAVAV tAVFL=tELFL tEHQZ tGHQZ VIH BYTE# F VOH DATA D/Q DQ0-DQ7 VOH DATA D/Q DQ8-DQ15 HIGH Z HIGH Z tELQV tGLQX tELQX tGLQV See Ordering Information for device speeds valid operational combinations . BYTE# should be in stable until determination of block erase, full chip erase, multi word/byte write, block lock- bit configuration or STS configuration success SR.7=1 . See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit High Seed Configuration for testing characteristics. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit Standard Configuration for testing characteristics. LHF16KA3 VIH ADDRESSES A VIH CE# E AIN tAVAV AIN tAVWH tWHAX VIL tELWL VIH OE# G tWHEH tWHGL VIH WE# W tWHWL tWHQV1,2,3,4 VIH DATA D/Q VIH BYTE# F High Z tPHWL tWLWH tDVWH tWHDX tFVWH Valid SRD tWHFV High Z STS R VIH WP# S tWHRL tSHWH tQVSL VIH RP# P VPPH1 tVPWH tQVVL VPP V VPPLK NOTES VCC power-up and standby. Write each setup command. Write each confirm command or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High. Figure AC Waveform for WE#-Controlled Write Operations LHF16KA3 ALTERNATIVE CE#-CONTROLLED WRITES 1 See Ordering Information for device speeds valid operational combinations . BYTE# should be in stable until determination of block erase, full chip erase, multi word/byte write, block lock- bit configuration or STS configuration success SR.7=1 . See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit High Seed Configuration for testing characteristics. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit Standard Configuration for testing characteristics. LHF16KA3 VIH ADDRESSES A VIH CE# E VIH OE# G tAVAV tAVEH tEHEL tELEH tDVEH tEHAX tEHGL VIH WE# W VIL tWLEL tEHWH tEHQV1,2,3,4 DATA D/Q VIH High Z tEHDX Valid SRD tPHEL tFVEH tEHFV BYTE# F High Z STS R VIH WP# S tEHRL tSHEH tQVSL VIH RP# P VPPH1 tVPEH tQVVL VPP V VPPLK NOTES VCC power-up and standby. Write each setup command. Write each confirm command or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High. Figure AC Waveform for CE#-Controlled Write Operations LHF16KA3 RESET OPERATIONS 7 ADDITIONAL INFORMATION Ordering Information Product line designator for all SHARP Flash products LH2 8F 16 0S5HT - L 7 0 Device Density 160 = 16-Mbit Architecture S = Regular Block Power Supply Type 5 = Smart 5 Technology Operating Temperature Blank = 0°C ~ +70°C H = -40°C ~ +85°C Access Speed ns 70:70ns 5V,30pF , 90ns 5V 10:100ns 5V Option Order Code 1 LH28F160S5HT-L70 Valid Operational Combinations VCC=5V±0.5V 100pF load, VCC=5V±0.25V 30pF load, TTL I/O Levels 1.5V I/O Levels LH28F160S5H-L90 LH28F160S5H-L70 A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC min VCC VIH RP# P RST# VIL VCCWH1/2 VPPH1/2 VCCW 2 V VIH ADDRESS A VIH CE# E VIH WE# W VIH OE# G VIH WP# S DATA VOH D/Q VOL t2VPH *1 tR or tF High Z tPHQV tAVQV Valid Address tELQV tR or tF tR tF tGLQV Valid Output

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PRODUCT SPECIFICATIONS

Integrated Circuits Group

LH28F160S5HT-L70

Flash Memory
16M 2MB x 8 / 1MB x 16

Model No. LHF16KA3

Spec No. EL127109B Issue Date March 21, 2001

LHF16KA3
●Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.
●When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions.
1 The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph 2 , even for the following application areas, be sure to observe the precautions given in Paragraph Never use the products for the equipment listed in Paragraph
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
2 Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system.
•Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
3 Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
4 Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales representative of the company.

LHF16KA3

CONTENTS
1 INTRODUCTION 3 Product 3
2 PRINCIPLES OF OPERATION 6 Data Protection 7
3 BUS 7 Read 7 Output Disable 7 Deep Power-Down 7 Read Identifier Codes Operation 8 Query 8
4 COMMAND DEFINITIONS 8 Read Array 11 Read Identifier Codes Command 11 Read Status Register Command....................... 11 Clear Status Register Command....................... 11 Query 12 Block Status Register 12 CFI Query Identification String..................... 13 System Interface Information....................... 13 Device Geometry Definition 14 SCS OEM Specific Extended Query Table 14 Block Erase 15 Full Chip Erase Command 15 Word/Byte Write Command............................... 16 Multi Word/Byte Write Command 16 Block Erase Suspend Command..................... 17 Multi Word/Byte Write Suspend Command... 17 Set Block Lock-Bit Command.......................... 18 Clear Block Lock-Bits Command..................... 18 STS Configuration Command 19
5 DESIGN CONSIDERATIONS Three-Line Output Control STS and Block Erase, Full Chip Erase, Multi Word/Byte Write and Block Lock-Bit Configuration Power Supply Decoupling VPP Trace on Printed Circuit Boards VCC, VPP, RP# Power-Up/Down Power Dissipation
6 ELECTRICAL Absolute Maximum Ratings Operating Conditions Capacitance AC Input/Output Test Conditions..................33 DC AC Characteristics - Read-Only Operations AC Characteristics - Write Operations..........39 Alternative CE#-Controlled Writes Reset Operations Block Erase, Full Chip Erase, Multi Word/Byte Write and Block Lock-Bit Configuration Performance...........................44
7 ADDITIONAL INFORMATION Ordering Information
8 PACKAGE AND PACKING SPECIFICATION........46

LHF16KA3

LH28F160S5HT-L70 16M-BIT 2MBx8/1MBx16 Smart 5 Flash MEMORY
• Smart 5 Technology 5V VCC 5V VPP
• Common Flash Interface CFI Universal & Upgradable Interface
• Scalable Command Set SCS
• High Speed Write Performance 32 Bytes x 2 plane Page Buffer 2µs/Byte Write Transfer Rate
• High Speed Read Performance 70ns 5V±0.25V , 90ns 5V±0.5V
• Operating Temperature -40°C to +85°C
• Enhanced Automated Suspend Options Write Suspend to Read Block Erase Suspend to Write Block Erase Suspend to Read
• High-Density Symmetrically-Blocked Architecture Thirty-two 64K-byte Erasable Blocks
• SRAM-Compatible Write Interface
• User-Configurable x8 or x16 Operation
• Enhanced Data Protection Features Absolute Protection with VPP=GND Flexible Block Locking Erase/Write Lockout during Power Transitions
• Extended Cycling Capability 100,000 Block Erase Cycles Million Block Erase Cycles/Chip
• Low Power Management Deep Power-Down Mode Automatic Power Savings Mode Decreases ICC in Static Mode
• Automated Write and Erase Command User Interface Status Register
• Industry-Standard Packaging 56-Lead TSOP
• ETOXTM* V Nonvolatile Flash Technology
• CMOS Process P-type silicon substrate
• Not designed or rated as radiation hardened

SHARP’s LH28F160S5HT-L70 Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S5HT-L70 offers three levels of protection absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs.

The LH28F160S5HT-L70 is conformed to the flash Scalable Command Set SCS and the Common Flash Interface CFI specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs.

The LH28F160S5HT-L70 is manufactured on SHARP’s 0.35µm ETOXTM* V process technology. It come in industry-standard package the 56-Lead TSOP, ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.

LHF16KA3
1 INTRODUCTION

This datasheet contains LH28F160S5HT-L70 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications.

Product Overview

The LH28F160S5HT-L70 is a high-performance 16Mbit Smart 5 Flash memory organized as 2MBx8/1MBx16. The 2MB of data is arranged in thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure

Smart 5 technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 5V VCC provides the highest read performance. VPP at 5V eliminates the need for a separate 12V converter,
while VPP=5V maximizes erase and write performance. In addition to flexible erase and
program voltages, the dedicated VPP pin gives complete data protection when

Table VCC and VPP Voltage Combinations Offered by Smart 5 Technology

VCC Voltage 5V

VPP Voltage 5V

Internal VCC and VPP detection Circuitry automatically configures the device for optimized read and write operations.

A Command User Interface CUI serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine WSM automatically executes the algorithms and timings necessary for block erase, full chip erase, multi word/byte write and block lock-bit configuration operations.

A block erase operation erases one of the device’s 64K-byte blocks typically within 0.34s 5V VCC, 5V VPP independent of other blocks. Each block can be independently erased 100,000 times million block erases per device . Block erase suspend mode allows system software to suspend block erase to read or write data from any other block.

A word/byte write is performed in byte increments typically within 9.24µs 5V VCC, 5V VPP . A multi word/byte write has high speed write performance of 2µs/byte 5V VCC, 5V VPP . Multi Word/byte write suspend mode enables the system to read data or
See Ordering Information for device speeds valid operational combinations .

See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit High Speed

Configuration for testing characteristics.

See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit Standard

Configuration for testing characteristics.

LHF16KA3

ADDRESSES A

VIH CE# E

VIH OE# G

VIH WE# W

VOH DATA D/Q

Standby HIGH Z

Device Address Selection

Address Stable

Data Valid tAVAV
tELQV tGLQX tELQX
tGLQV
tAVQV

Valid Output
tEHQZ tGHQZ
tOH HIGH Z

VIH RP# P
tPHQV

NOTE CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.

Figure AC Waveform for Read Operations

LHF16KA3

ADDRESSES A

VIH CE# E

VIH OE# G

Standby

Device Address Selection

Address Stable

Data Valid tAVAV
tAVFL=tELFL
tEHQZ tGHQZ

VIH BYTE# F

VOH DATA D/Q DQ0-DQ7

VOH DATA D/Q DQ8-DQ15

HIGH Z HIGH Z
tELQV tGLQX tELQX
tGLQV
See Ordering Information for device speeds valid operational combinations .

BYTE# should be in stable until determination of block erase, full chip erase, multi word/byte write, block lock-
bit configuration or STS configuration success SR.7=1 .

See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit High Seed

Configuration for testing characteristics.

See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit Standard

Configuration for testing characteristics.

LHF16KA3

VIH ADDRESSES A

VIH CE# E

AIN tAVAV

AIN tAVWH
tWHAX

VIL tELWL

VIH OE# G
tWHEH
tWHGL

VIH WE# W
tWHWL
tWHQV1,2,3,4

VIH DATA D/Q

VIH BYTE# F

High Z tPHWL
tWLWH tDVWH
tWHDX
tFVWH

Valid SRD
tWHFV

High Z STS R

VIH WP# S
tWHRL tSHWH
tQVSL

VIH RP# P

VPPH1
tVPWH
tQVVL

VPP V VPPLK

NOTES VCC power-up and standby. Write each setup command. Write each confirm command or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.

Figure AC Waveform for WE#-Controlled Write Operations

LHF16KA3

ALTERNATIVE CE#-CONTROLLED WRITES 1
See Ordering Information for device speeds valid operational combinations .

BYTE# should be in stable until determination of block erase, full chip erase, multi word/byte write, block lock-
bit configuration or STS configuration success SR.7=1 .

See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit High Seed

Configuration for testing characteristics.

See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit Standard

Configuration for testing characteristics.

LHF16KA3

VIH ADDRESSES A

VIH CE# E

VIH OE# G
tAVAV
tAVEH
tEHEL
tELEH tDVEH
tEHAX tEHGL

VIH WE# W

VIL tWLEL
tEHWH
tEHQV1,2,3,4

DATA D/Q VIH High Z
tEHDX

Valid SRD
tPHEL
tFVEH
tEHFV

BYTE# F

High Z STS R

VIH WP# S
tEHRL tSHEH
tQVSL

VIH RP# P

VPPH1
tVPEH
tQVVL

VPP V VPPLK

NOTES VCC power-up and standby. Write each setup command. Write each confirm command or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command.

CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.

Figure AC Waveform for CE#-Controlled Write Operations

LHF16KA3

RESET OPERATIONS
7 ADDITIONAL INFORMATION Ordering Information

Product line designator for all SHARP Flash products

LH2 8F 16 0S5HT - L 7 0

Device Density 160 = 16-Mbit

Architecture S = Regular Block

Power Supply Type 5 = Smart 5 Technology

Operating Temperature Blank = 0°C ~ +70°C H = -40°C ~ +85°C

Access Speed ns 70:70ns 5V,30pF , 90ns 5V 10:100ns 5V

Option

Order Code
1 LH28F160S5HT-L70

Valid Operational Combinations

VCC=5V±0.5V 100pF load,

VCC=5V±0.25V 30pF load,

TTL I/O Levels
1.5V I/O Levels

LH28F160S5H-L90

LH28F160S5H-L70

A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up

AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.

VCC min VCC

VIH RP# P RST# VIL

VCCWH1/2

VPPH1/2 VCCW *2 V

VIH ADDRESS A

VIH CE# E

VIH WE# W

VIH OE# G

VIH WP# S

DATA

VOH D/Q VOL
t2VPH *1
tR or tF

High Z
tPHQV
tAVQV

Valid Address
tELQV
tR or tF tR
tF tGLQV

Valid Output

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Datasheet ID: LH28F160S5HT-L70 515941