CY7C1312BV18-200BZC

CY7C1312BV18-200BZC Datasheet


CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18

Part Datasheet
CY7C1312BV18-200BZC CY7C1312BV18-200BZC CY7C1312BV18-200BZC (pdf)
Related Parts Information
CY7C1314BV18-250BZXC CY7C1314BV18-250BZXC CY7C1314BV18-250BZXC
CY7C1314BV18-167BZC CY7C1314BV18-167BZC CY7C1314BV18-167BZC
CY7C1314BV18-167BZI CY7C1314BV18-167BZI CY7C1314BV18-167BZI
CY7C1312BV18-167BZCT CY7C1312BV18-167BZCT CY7C1312BV18-167BZCT
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CY7C1312BV18-167BZI CY7C1312BV18-167BZI CY7C1312BV18-167BZI
CY7C1312BV18-200BZI CY7C1312BV18-200BZI CY7C1312BV18-200BZI
CY7C1312BV18-200BZXC CY7C1312BV18-200BZXC CY7C1312BV18-200BZXC
CY7C1312BV18-250BZC CY7C1312BV18-250BZC CY7C1312BV18-250BZC
CY7C1314BV18-250BZC CY7C1314BV18-250BZC CY7C1314BV18-250BZC
CY7C1312BV18-167BZC CY7C1312BV18-167BZC CY7C1312BV18-167BZC
PDF Datasheet Preview
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18
18-Mbit QDR -II SRAM 2-Word Burst Architecture
• Separate independent read and write data ports Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 2-word burst on all accesses
• Double Data Rate DDR interfaces on both read and write ports
data transferred at 500 MHz at 250 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high-speed
systems
• Single multiplexed address input bus latches address inputs
for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V ±0.1V IO VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• Variable drive HSTL output buffers
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

CY7C1310BV18 2M x 8 CY7C1910BV18 2M x 9 CY7C1312BV18 1M x 18 CY7C1314BV18 512K x 36

Selection Guide

Maximum Operating Frequency

Maximum Operating Current
250 MHz 250 735 800 900

Functional Description

The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 8-bit words CY7C1310BV18 , 9-bit words CY7C1910BV18 , 18-bit words CY7C1312BV18 , or 36-bit words CY7C1314BV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
200 MHz 200 630 675 750
167 MHz 167 550 600 650

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
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Logic Block Diagram CY7C1310BV18

CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18

D[7:0]

A 19:0 20

Address Register

K DOFF

VREF WPS NWS[1:0]

CLK Gen.

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg

Address Register

A 19:0
1M x 8 Array 1M x 8 Array

Read Data Reg. 16 8

Control Logic
Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1310BV18-250BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1910BV18-250BZC

CY7C1312BV18-250BZC

CY7C1314BV18-250BZC

CY7C1310BV18-250BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1910BV18-250BZXC

CY7C1312BV18-250BZXC

CY7C1314BV18-250BZXC

CY7C1310BV18-250BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1910BV18-250BZI

CY7C1312BV18-250BZI

CY7C1314BV18-250BZI

CY7C1310BV18-250BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1910BV18-250BZXI

CY7C1312BV18-250BZXI

CY7C1314BV18-250BZXI
200 CY7C1310BV18-200BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1910BV18-200BZC

CY7C1312BV18-200BZC

CY7C1314BV18-200BZC

CY7C1310BV18-200BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1910BV18-200BZXC

CY7C1312BV18-200BZXC

CY7C1314BV18-200BZXC

CY7C1310BV18-200BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1910BV18-200BZI
Ordering Information continued

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1310BV18-167BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1910BV18-167BZC

CY7C1312BV18-167BZC

CY7C1314BV18-167BZC

CY7C1310BV18-167BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1910BV18-167BZXC

CY7C1312BV18-167BZXC

CY7C1314BV18-167BZXC

CY7C1310BV18-167BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1910BV18-167BZI

CY7C1312BV18-167BZI

CY7C1314BV18-167BZI

CY7C1310BV18-167BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1910BV18-167BZXI

CY7C1312BV18-167BZXI

CY7C1314BV18-167BZXI

Page 26 of 29 [+] Feedback

CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B - 01.0665X
11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M N P R
0.15 4X
SYT Removed CY7C1910BV18 from the title Included 300 MHz Speed Bin Added Industrial Temperature Grade Replaced TBDs for IDD and ISB1 specifications Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 28.51°C/W and ΘJC = 5.91°C/W Replaced TBDs in the Capacitance Table for the 165 FBGA Package Changed the package diagram from BB165E 15 x 17 x mm to BB165D 13 x 15 x mm Added Pb-Free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per availability
*B 413997 See ECN
Converted from Preliminary to Final Added CY7C1910BV18 part number to the title Removed 300MHz Speed Bin Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed C/C Pin Description in the features section and Pin Description Corrected Typo in Identification Register Definitions for CY7C1910BV18 on page# 16 Added power up sequence details and waveforms Added foot notes #15, 16, and 17 on page# 18 Replaced Three state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 13 Modified the IDD and ISB values Modified test condition in Footnote #20 on page# 19 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table
*C 423334 See ECN *D 472384 See ECN

Changed the IEEE Standard # to Changed the Minimum Value of tSC and tHC from 0.5ns to 0.35ns for 250 MHz and ns to ns for 200 MHz speed bins Changed the description of tSA from K Clock Rise to Clock K/K Rise Changed the description of tSC and tHC from Clock K and K Rise to K Clock Rise
Modified the ZQ Definition from Alternately, this pin is connected directly to VDD to Alternately, this pin is connected directly to VDDQ Changed the IEEE Standard # from to Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in Tap Switching Characteristics. Modified Power Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from to +85°C to +125°C Added additional notes in the AC parameter section Modified AC Switching Waveform Corrected the typo In the Tap Switching Characteristics. Updated the Ordering Information Table

Page 28 of 29 [+] Feedback

CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18

Document History Page

Document Title 18-Mbit QDR -II SRAM 2-Word Burst Architecture Document Number 38-05619
*E 1274723 See ECN

VKN Corrected typo in the JTAG ID code for CY7C1910BV18
*F 2511674
06/03/08

VKN/PYRS Updated Logic Block diagrams Updated IDD/ISB specs Added footnote# 19 related to IDD Updated power up sequence waveform and its description Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed ΘJA spec from to Changed ΘJC spec from to Changed tCYC maximum spec to ns for all speed bins Modified footnotes 21 and 28

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
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General
psoc.cypress.com/solutions

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psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
psoc.cypress.com/usb

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 29 of 29

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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More datasheets: 18026ACU | FGPF7N60RUFDTU | FAN5032MPX | PANH 104450 | CY7C1314BV18-250BZXC | CY7C1314BV18-167BZC | CY7C1314BV18-167BZI | CY7C1312BV18-167BZCT | CY7C1314BV18-200BZC | CY7C1312BV18-167BZI


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Datasheet ID: CY7C1312BV18-200BZC 507950