CY7C1315BV18-250BZC

CY7C1315BV18-250BZC Datasheet

CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18

Part	Datasheet
CY7C1315BV18-250BZC	CY7C1315BV18-250BZC (pdf)

Related Parts	Information
CY7C1315BV18-167BZCT	CY7C1315BV18-167BZCT
CY7C1313BV18-167BZCT	CY7C1313BV18-167BZCT
CY7C1313BV18-200BZC	CY7C1313BV18-200BZC
CY7C1313BV18-250BZC	CY7C1313BV18-250BZC
CY7C1315BV18-200BZXI	CY7C1315BV18-200BZXI
CY7C1315BV18-200BZI	CY7C1315BV18-200BZI
CY7C1313BV18-167BZC	CY7C1313BV18-167BZC
CY7C1315BV18-167BZC	CY7C1315BV18-167BZC
CY7C1315BV18-200BZC	CY7C1315BV18-200BZC
CY7C1315BV18-250BZXC	CY7C1315BV18-250BZXC
CY7C1315BV18-200BZXC	CY7C1315BV18-200BZXC

PDF Datasheet Preview
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Functional Description • Separate Independent Read and Write data ports Supports concurrent transactions • 300-MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate DDR interfaces on both Read and Write ports data transferred at 600 MHz at 300 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock-skew and flight-time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in x 8, x 9, x 18, and x 36 configurations • Full data coherency providing most current data • Core VDD = ±0.1V I/O VDDQ = 1.4V to VDD • Available in 165-ball FBGA package 13 x 15 x mm • Offered in both lead-free and non-lead free packages • Variable drive HSTL output buffers • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations CY7C1311BV18 2M x 8 CY7C1911BV18 2M x 9 CY7C1313BV18 1M x 18 CY7C1315BV18 512K x 36 The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate DDR interfaces. Each address location is associated with four 8-bit words CY7C1311BV18 or 9-bit words CY7C1911BV18 or 18-bit words CY7C1313BV18 or 36-bit words CY7C1315BV18 that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Maximum Operating Frequency Maximum Operating Current 300 MHz 300 550 278 MHz 278 530 250 MHz 250 500 200 MHz 200 450 167 MHz 167 400 Unit MHz mA Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Logic Block Diagram CY7C1311BV18 D[7:0] 8 A 18:0 19 Address Register Write Reg Address Register 19 A 18:0 Write Add. Decode Read Add. Decode 512K x 8 Array 512K x 8 Array 512K x 8 Array 512K x 8 Array DOFF VREF WPS NWS[1:0] CLK Gen. Control Logic Read Data Reg. 32 16 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1311BV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1911BV18-167BZC CY7C1313BV18-167BZC CY7C1315BV18-167BZC CY7C1311BV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1911BV18-167BZXC CY7C1313BV18-167BZXC CY7C1315BV18-167BZXC CY7C1311BV18-167BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1911BV18-167BZI CY7C1313BV18-167BZI CY7C1315BV18-167BZI CY7C1311BV18-167BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1911BV18-167BZXI CY7C1313BV18-167BZXI CY7C1315BV18-167BZXI 200 CY7C1311BV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1911BV18-200BZC CY7C1313BV18-200BZC CY7C1315BV18-200BZC CY7C1311BV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1911BV18-200BZXC CY7C1313BV18-200BZXC CY7C1315BV18-200BZXC CY7C1311BV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1911BV18-200BZI CY7C1313BV18-200BZI CY7C1315BV18-200BZI CY7C1311BV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1911BV18-200BZXI CY7C1313BV18-200BZXI CY7C1315BV18-200BZXI 250 CY7C1311BV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1311BV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1911BV18-250BZI CY7C1313BV18-250BZI CY7C1315BV18-250BZI CY7C1311BV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1911BV18-250BZXI CY7C1313BV18-250BZXI CY7C1315BV18-250BZXI 278 CY7C1311BV18-278BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1911BV18-278BZC CY7C1313BV18-278BZC CY7C1315BV18-278BZC CY7C1311BV18-278BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1911BV18-278BZXC CY7C1313BV18-278BZXC CY7C1315BV18-278BZXC CY7C1311BV18-278BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1911BV18-278BZI CY7C1313BV18-278BZI CY7C1315BV18-278BZI CY7C1311BV18-278BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1911BV18-278BZXI CY7C1313BV18-278BZXI CY7C1315BV18-278BZXI 300 CY7C1311BV18-300BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1911BV18-300BZC CY7C1313BV18-300BZC CY7C1315BV18-300BZC CY7C1311BV18-300BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1911BV18-300BZXC CY7C1313BV18-300BZXC CY7C1315BV18-300BZXC CY7C1311BV18-300BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Updated the Ordering Information by Shading and Unshading MPNs as per availability 413997 See ECN NXR Converted from Preliminary to Final Added CY7C1911BV18 to the title Added 278-MHz speed Bin Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed C/C Description in the features section Added power-up sequence details and waveforms Added foot notes# 17, 18, 19 on page# 19 Changed the description of IX from Input Load Current to Input Leakage Current on page# 20 Modified the IDD and ISB values Modified test condition in Footnote # 22 on page# 20 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table 472384 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from to +85°C to +125°C Added additional notes in the AC parameter section Modified AC Switching Waveform Corrected the typo In the AC Switching Characteristics Table Updated the Ordering Information Table Page 28 of 28 [+] Feedback

PDF Datasheet Preview

CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
18-Mbit QDR -II SRAM 4-Word Burst Architecture

Functional Description
• Separate Independent Read and Write data ports Supports concurrent transactions
• 300-MHz clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate DDR interfaces on both Read and

Write ports data transferred at 600 MHz at 300 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize
clock-skew and flight-time mismatches
• Echo clocks CQ and CQ simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x 8, x 9, x 18, and x 36 configurations
• Full data coherency providing most current data
• Core VDD = ±0.1V I/O VDDQ = 1.4V to VDD
• Available in 165-ball FBGA package 13 x 15 x mm
• Offered in both lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

CY7C1311BV18 2M x 8 CY7C1911BV18 2M x 9 CY7C1313BV18 1M x 18 CY7C1315BV18 512K x 36

The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate DDR interfaces. Each address location is associated with four 8-bit words CY7C1311BV18 or 9-bit words CY7C1911BV18 or 18-bit words CY7C1313BV18 or 36-bit words CY7C1315BV18 that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Maximum Operating Frequency Maximum Operating Current
300 MHz 300 550
278 MHz 278 530
250 MHz 250 500
200 MHz 200 450
167 MHz 167 400

Unit MHz mA

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18

Logic Block Diagram CY7C1311BV18

D[7:0] 8

A 18:0 19

Address Register

Write Reg

Address Register
19 A 18:0

Write Add. Decode Read Add. Decode
512K x 8 Array 512K x 8 Array 512K x 8 Array 512K x 8 Array

DOFF

VREF WPS NWS[1:0]

CLK Gen.

Control Logic

Read Data Reg. 32 16
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1311BV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1911BV18-167BZC

CY7C1313BV18-167BZC

CY7C1315BV18-167BZC

CY7C1311BV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1911BV18-167BZXC

CY7C1313BV18-167BZXC

CY7C1315BV18-167BZXC

CY7C1311BV18-167BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1911BV18-167BZI

CY7C1313BV18-167BZI

CY7C1315BV18-167BZI

CY7C1311BV18-167BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1911BV18-167BZXI

CY7C1313BV18-167BZXI

CY7C1315BV18-167BZXI
200 CY7C1311BV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1911BV18-200BZC

CY7C1313BV18-200BZC

CY7C1315BV18-200BZC

CY7C1311BV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1911BV18-200BZXC

CY7C1313BV18-200BZXC

CY7C1315BV18-200BZXC

CY7C1311BV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1911BV18-200BZI

CY7C1313BV18-200BZI

CY7C1315BV18-200BZI

CY7C1311BV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1911BV18-200BZXI

CY7C1313BV18-200BZXI

CY7C1315BV18-200BZXI
250 CY7C1311BV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1311BV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1911BV18-250BZI

CY7C1313BV18-250BZI

CY7C1315BV18-250BZI

CY7C1311BV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1911BV18-250BZXI

CY7C1313BV18-250BZXI

CY7C1315BV18-250BZXI
278 CY7C1311BV18-278BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1911BV18-278BZC

CY7C1313BV18-278BZC

CY7C1315BV18-278BZC

CY7C1311BV18-278BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1911BV18-278BZXC

CY7C1313BV18-278BZXC

CY7C1315BV18-278BZXC

CY7C1311BV18-278BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1911BV18-278BZI

CY7C1313BV18-278BZI

CY7C1315BV18-278BZI

CY7C1311BV18-278BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1911BV18-278BZXI

CY7C1313BV18-278BZXI

CY7C1315BV18-278BZXI
300 CY7C1311BV18-300BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1911BV18-300BZC

CY7C1313BV18-300BZC

CY7C1315BV18-300BZC

CY7C1311BV18-300BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1911BV18-300BZXC

CY7C1313BV18-300BZXC

CY7C1315BV18-300BZXC

CY7C1311BV18-300BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
413997 See ECN NXR Converted from Preliminary to Final

Added CY7C1911BV18 to the title

Added 278-MHz speed Bin

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Changed C/C Description in the features section

Added power-up sequence details and waveforms

Added foot notes# 17, 18, 19 on page# 19

Changed the description of IX from Input Load Current to Input Leakage Current on page# 20
Modified the IDD and ISB values Modified test condition in Footnote # 22 on page# 20 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering

Information table
Updated Ordering Information Table
472384 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly
to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table

Modified Power-Up waveform

Changed the Maximum rating of Ambient Temperature with Power Applied
from to +85°C to +125°C

Added additional notes in the AC parameter section

Modified AC Switching Waveform

Corrected the typo In the AC Switching Characteristics Table
Updated the Ordering Information Table

Page 28 of 28 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1315BV18-250BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1315BV18-250BZC 507949