CY7C1308DV25C-167BZCT

CY7C1308DV25C-167BZCT Datasheet

CY7C1308DV25C

Part	Datasheet
CY7C1308DV25C-167BZCT	CY7C1308DV25C-167BZCT (pdf)

Related Parts	Information
CY7C1308DV25C-167BZC	CY7C1308DV25C-167BZC

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CY7C1308DV25C 9 Mbit DDR I SRAM 4-Word Burst Architecture • 9 Mbit Density 256 Kbit x 36 • 250 MHz Clock for High Bandwidth • 4-Word Burst to Reduce Address Bus Frequency • Double Data Rate DDR Interfaces data transferred at 500 MHz at 250 MHz • Two Input Clocks K and K for Precise DDR uses rising edges only • Two Input Clocks C and C Account for Clock Skew and Flight Time Mismatching • Separate Port Selects for Depth Expansion • Synchronous Internally Self-timed Writes • 2.5V Core Power Supply with HSTL Inputs and Outputs • Variable Drive HSTL Output Buffers • Expanded HSTL Output Voltage 1.4V to 1.9V • 13 x 15 x mm pitch fBGA package, 165 ball 11 x 15 matrix • JTAG Compatible Test Access Port Configuration CY7C1308DV25C 256K x 36 Logic Block Diagram Functional Description The CY7C1308DV25C is a 2.5V Synchronous Pipelined SRAM equipped with DDR I Double Data Rate architecture. The DDR I architecture consists of an SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Every Read or Write operation is associated with four words that burst sequentially into or out of the device. The burst counter takes in the least two significant bits of the external address and bursts four 36-bit words. Depth expansion is accomplished with Port Selects for each port. Port Selects allow each port to operate independently. Asynchronous inputs include impedance match ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C/C are also provided for maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self timed write circuitry. A 1:0 Burst Logic 18 16 A 17:0 A 17:2 Address Register CLK Gen. Vref R/W Control Logic Write Add. Decode Read Add. Decode Write Reg 256K x 36 Array Read Data Reg. 144 72 Output Logic Control Reg. Reg. Reg. CQ DQ[35:0] • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1308DV25C Selection Guide Parameter Maximum Operating Frequency Maximum Operating Current Shaded areas contain advance information. Pin Configuration 250 MHz 250 850 200 MHz 200 700 Ordering Information Speed MHz Ordering Code Package Name Package Type 250 CY7C1308DV25C-250BZC BB165D 13 x 15 x mm FBGA 200 CY7C1308DV25C-200BZC BB165D 13 x 15 x mm FBGA 167 CY7C1308DV25C-167BZC BB165D 13 x 15 x mm FBGA Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts. Package Diagram Figure 165 FBGA 13 x 15 x mm BB165D Operating Range Commercial Commercial Commercial 51-85180 *B Page 17 of 18 [+] Feedback CY7C1308DV25C Document History Page Document Title CY7C1308DV25C 9 Mbit DDR I SRAM 4-Word Burst Architecture Document Number 001-04310 ECN No. Submission Date Orig. of Change Description of Change 397842 See ECN SYT New Data Sheet 2748172 08/04/09 NJY/PYRS Updated template Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document are the trademarks of their respective holders.

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CY7C1308DV25C
9 Mbit DDR I SRAM 4-Word Burst Architecture
• 9 Mbit Density 256 Kbit x 36
• 250 MHz Clock for High Bandwidth
• 4-Word Burst to Reduce Address Bus Frequency
• Double Data Rate DDR Interfaces
data transferred at 500 MHz at 250 MHz
• Two Input Clocks K and K for Precise DDR
uses rising edges only
• Two Input Clocks C and C Account for Clock Skew and Flight

Time Mismatching
• Separate Port Selects for Depth Expansion
• Synchronous Internally Self-timed Writes
• 2.5V Core Power Supply with HSTL Inputs and Outputs
• Variable Drive HSTL Output Buffers
• Expanded HSTL Output Voltage 1.4V to 1.9V
• 13 x 15 x mm pitch fBGA package, 165 ball 11 x
15 matrix
• JTAG Compatible Test Access Port

Configuration

CY7C1308DV25C 256K x 36

Logic Block Diagram

Functional Description

The CY7C1308DV25C is a 2.5V Synchronous Pipelined SRAM equipped with DDR I Double Data Rate architecture. The DDR I architecture consists of an SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Every Read or Write operation is associated with four words that burst sequentially into or out of the device. The burst counter takes in the least two significant bits of the external address and bursts four 36-bit words. Depth expansion is accomplished with Port Selects for each port. Port Selects allow each port to operate independently.

Asynchronous inputs include impedance match ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C/C are also provided for maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self timed write circuitry.

A 1:0

Burst Logic
18 16

A 17:0

A 17:2

Address Register

CLK Gen.

Vref R/W

Control Logic

Write Add. Decode Read Add. Decode

Write Reg
256K x 36 Array

Read Data Reg. 144 72

Output Logic

Control

Reg. Reg.

Reg.

CQ DQ[35:0]
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1308DV25C

Selection Guide

Parameter Maximum Operating Frequency Maximum Operating Current

Shaded areas contain advance information.

Pin Configuration
250 MHz 250 850
200 MHz 200 700
Ordering Information

Speed MHz
Ordering Code

Package Name

Package Type
250 CY7C1308DV25C-250BZC

BB165D 13 x 15 x mm FBGA
200 CY7C1308DV25C-200BZC

BB165D 13 x 15 x mm FBGA
167 CY7C1308DV25C-167BZC

BB165D 13 x 15 x mm FBGA

Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts.

Package Diagram

Figure 165 FBGA 13 x 15 x mm BB165D

Operating Range

Commercial

Commercial

Commercial
51-85180 *B

Page 17 of 18 [+] Feedback

CY7C1308DV25C

Document History Page

Document Title CY7C1308DV25C 9 Mbit DDR I SRAM 4-Word Burst Architecture Document Number 001-04310

ECN No.

Submission Date

Orig. of Change

Description of Change
397842

See ECN

SYT New Data Sheet
2748172
08/04/09

NJY/PYRS Updated template

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document are the trademarks of their respective holders.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1308DV25C-167BZCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1308DV25C-167BZCT 507948