CY7C1305BV25-167BZC

CY7C1305BV25-167BZC Datasheet

CY7C1305BV25 CY7C1307BV25

Part	Datasheet
CY7C1305BV25-167BZC	CY7C1305BV25-167BZC (pdf)

Related Parts	Information
CY7C1305BV25-167BZCT	CY7C1305BV25-167BZCT

PDF Datasheet Preview
CY7C1305BV25 CY7C1307BV25 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture Functional Description • Separate independent Read and Write data ports • Supports concurrent transactions • 167-MHz clock for high bandwidth • ns Clock-to-Valid access time • 4-Word Burst for reducing the address bus frequency • Double Data Rate DDR interfaces on both Read and Write Ports data transferred at 333 MHz • Two input clocks K and K for precise DDR timing • SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock-skew and flight-time mismatches. • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL Inputs and Outputs • Available in 165-ball FBGA package 13 x 15 x mm • Variable drive HSTL output buffers • Expanded HSTL output voltage • JTAG interface Configurations The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous Pipelined SRAMs equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input K clock. Accesses to the device’s Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate DDR interfaces. Each address location is associated with four 18-bit words CY7C1305BV25 and four 36-bit words CY7C1307BV25 that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks K/K and C/C memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. • CY7C1305BV25 1M x 18 • CY7C1307BV25 512K x 36 Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1305BV25 D[17:0] 18 A[17:0] 18 Address Register Write Reg 256Kx18 Array 256Kx18 Array 256Kx18 Array 256Kx18 Array Gen. Vref WPS BWS[0:1] Control Logic Read Data Reg. 72 36 Write Add. Decode Read Add. Decode CY7C1305BV25 CY7C1307BV25 Address Register 18 A 17:0 Control Logic Reg. Reg. Reg. 18 18 Q[17:0] Logic Block Diagram CY7C1307BV25 D[35:0] A 16:0 17 36 Address Register Write Reg Address Register 17 A 16:0 Write Add. Decode Read Add. Decode 128K x 36 Array 128K x 36 Array 128K x 36 Array 128K x 36 Array Gen. Vref WPS BWS[0:3] Control Logic Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at t Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1305BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial Package Diagram 51-85180 *C Page 20 of 21 [+] Feedback CY7C1305BV25 CY7C1307BV25 Document History Page Document Title CY7C1305BV25/CY7C1307BV25 18-Mbit Burst of Four Pipelined SRAM with QDR Architecture Document Number 38-05630 Submission Orig. of ECN NO. Change Description of Change 253049 See ECN SYT New Data Sheet 436864 See ECN NXR Converted from Preliminary to Final. Removed 133 MHz & 100 MHz from product offering. Included industrial Operating Range. Changed C/C Description in the Features Section & Pin Description Table. Changed tTCYC from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz and changed tTH and tTL from 40 ns to 20 ns in TAP AC Switching Characteristics table Modified the ZQ pin definition as follows: Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD. Modified the Description of IX from Input Load current to Input Leakage Current on page # Modified test condition in note# 16 from VDDQ < VDD to VDDQ VDD Updated the Ordering Information table and replaced the Package Name Column with Package Diagram. 2896654 03/20/2010 NJY Removed inactive parts from Ordering Information table Updated package diagram. Quad Data Rate SRAM and QDRSRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 21 of 21 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback

PDF Datasheet Preview

CY7C1305BV25 CY7C1307BV25
18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture

Functional Description
• Separate independent Read and Write data ports
• Supports concurrent transactions
• 167-MHz clock for high bandwidth
• ns Clock-to-Valid access time
• 4-Word Burst for reducing the address bus frequency
• Double Data Rate DDR interfaces on both Read and

Write Ports data transferred at 333 MHz
• Two input clocks K and K for precise DDR timing
• SRAM uses rising edges only
• Two input clocks for output data C and C to minimize
clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• Available in 165-ball FBGA package 13 x 15 x mm
• Variable drive HSTL output buffers
• Expanded HSTL output voltage
• JTAG interface

Configurations

The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous Pipelined SRAMs equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input K clock. Accesses to the device’s Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate DDR interfaces. Each address location is associated with four 18-bit words CY7C1305BV25 and four 36-bit words CY7C1307BV25 that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks K/K and C/C memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
• CY7C1305BV25 1M x 18
• CY7C1307BV25 512K x 36

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1305BV25

D[17:0] 18

A[17:0] 18

Address Register

Write Reg
256Kx18 Array 256Kx18 Array 256Kx18 Array 256Kx18 Array

Gen.

Vref WPS BWS[0:1]

Control Logic

Read Data Reg. 72 36

Write Add. Decode Read Add. Decode

CY7C1305BV25 CY7C1307BV25

Address Register
18 A 17:0

Control Logic

Reg. Reg.

Reg. 18
18 Q[17:0]

Logic Block Diagram CY7C1307BV25

D[35:0] A 16:0 17
36 Address Register

Write Reg

Address Register
17 A 16:0

Write Add. Decode Read Add. Decode
128K x 36 Array 128K x 36 Array 128K x 36 Array 128K x 36 Array

Gen.

Vref WPS BWS[0:3]

Control Logic
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at t

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1305BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

Package Diagram
51-85180 *C

Page 20 of 21 [+] Feedback

CY7C1305BV25 CY7C1307BV25

Document History Page

Document Title CY7C1305BV25/CY7C1307BV25 18-Mbit Burst of Four Pipelined SRAM with QDR Architecture Document Number 38-05630

Submission Orig. of

ECN NO.

Change

Description of Change
253049 See ECN

SYT New Data Sheet
436864 See ECN

NXR Converted from Preliminary to Final.

Removed 133 MHz & 100 MHz from product offering.

Included industrial Operating Range.

Changed C/C Description in the Features Section & Pin Description Table.

Changed tTCYC from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz and changed tTH and tTL from 40 ns to 20 ns in TAP AC Switching Characteristics table

Modified the ZQ pin definition as follows:

Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode

Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD. Modified the Description of IX from Input Load current to Input Leakage Current on page #
Modified test condition in note# 16 from VDDQ < VDD to VDDQ VDD Updated the Ordering Information table and replaced the Package Name

Column with Package Diagram.
2896654 03/20/2010
NJY Removed inactive parts from Ordering Information table Updated package
diagram.

Quad Data Rate SRAM and QDRSRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 21 of 21

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1305BV25-167BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1305BV25-167BZC 507947