CY7C1297H-133AXC

CY7C1297H-133AXC Datasheet

CY7C1297H

Part	Datasheet
CY7C1297H-133AXC	CY7C1297H-133AXC (pdf)

PDF Datasheet Preview
CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM • 64K x 18 common I/O • 3.3V core power supply VDD • 2.5V/3.3V I/O power supply VDDQ • Fast clock-to-output times ns for 133-MHz version • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Available in JEDEC-standard lead-free 100-Pin TQFP package • “ZZ” Sleep Mode option Logic Block Diagram Functional Description[1] The CY7C1297H is a 64K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CCoEn1tr o, ldeinppthu-tesxp AanDsSioCn, Chip Enables ADSP, and A CDEV2 , aWndriCteE3E ,naBbulresst BW[A:B], and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. The CY7C1297H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . The CY7C1297H operates from a +3.3V core power supply while all outputs may operate either with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. A0,A1,A MODE ADV CLK ADSC ADSP BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A[1:0] BURST Q1 COUNTER AND LOGIC DQB,DQPB WRITE REGISTER DQA,DQPA WRITE REGISTER ENABLE REGISTER DQB,DQPB WRITE DRIVER DQA,DQPA WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at t Speed MHz Ordering Code 133 CY7C1297H-133AXC Package Diagram Package Diagram Package Type 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Operating Range Commercial 51-85050 *C Page 14 of 15 [+] Feedback CY7C1297H Document History Document Title CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM Document Number 38-05669 Orig. of ECN NO. Issue Date Change Description of Change 345879 See ECN PCI New Data Sheet 430677 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added 2.5VI/O option Changed Three-State to Tri-State Included Maximum Ratings for VDDQ relative to GND Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Modified test condition from VIH < VDD to VIH VDD Replaced Package Name column with Package Diagram in the Ordering Information table 482139 See ECN VKN Converted from Preliminary to Final. Updated the Ordering Information table. 2896202 03/19/2010 NJY Removed Inactvie parts from the Ordering Information table Updated package diagram. Page 15 of 15 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback

PDF Datasheet Preview

CY7C1297H
1-Mbit 64K x 18 Flow-Through Sync SRAM
• 64K x 18 common I/O
• 3.3V core power supply VDD
• 2.5V/3.3V I/O power supply VDDQ
• Fast clock-to-output times
ns for 133-MHz version
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel

Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• “ZZ” Sleep Mode option

Logic Block Diagram

Functional Description[1]

The CY7C1297H is a 64K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
ns 133-MHz version . A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered

Clock Input CLK . The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable

CCoEn1tr o, ldeinppthu-tesxp AanDsSioCn,

Chip Enables ADSP, and

A CDEV2 , aWndriCteE3E ,naBbulresst

BW[A:B], and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

The CY7C1297H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

The CY7C1297H operates from a +3.3V core power supply while all outputs may operate either with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

A0,A1,A

MODE ADV CLK

ADSC ADSP

BWA BWE GW

CE1 CE2 CE3 OE

ADDRESS REGISTER

A[1:0]

BURST Q1 COUNTER AND

LOGIC

DQB,DQPB WRITE REGISTER

DQA,DQPA WRITE REGISTER

ENABLE REGISTER

DQB,DQPB WRITE DRIVER

DQA,DQPA WRITE DRIVER

MEMORY ARRAY

SENSE AMPS

OUTPUT BUFFERS
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at t

Speed MHz
Ordering Code
133 CY7C1297H-133AXC

Package Diagram

Package Diagram

Package Type
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Operating Range

Commercial
51-85050 *C

Page 14 of 15 [+] Feedback

CY7C1297H

Document History

Document Title CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM Document Number 38-05669

Orig. of ECN NO. Issue Date Change

Description of Change
345879 See ECN

PCI New Data Sheet
430677 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Added 2.5VI/O option

Changed Three-State to Tri-State

Included Maximum Ratings for VDDQ relative to GND Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table
Modified test condition from VIH < VDD to VIH VDD Replaced Package Name column with Package Diagram in the Ordering

Information table
482139 See ECN

VKN Converted from Preliminary to Final.
Updated the Ordering Information table.
2896202 03/19/2010 NJY Removed Inactvie parts from the Ordering Information table Updated
package diagram.

Page 15 of 15

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1297H-133AXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1297H-133AXC 507940