CY7C12481KV18-400BZXC

CY7C12481KV18-400BZXC Datasheet

CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18

Part	Datasheet
CY7C12481KV18-400BZXC	CY7C12481KV18-400BZXC (pdf)

Related Parts	Information
CY7C12501KV18-400BZXC	CY7C12501KV18-400BZXC
CY7C12501KV18-400BZC	CY7C12501KV18-400BZC
CY7C12501KV18-450BZXC	CY7C12501KV18-450BZXC
CY7C12481KV18-400BZC	CY7C12481KV18-400BZC

PDF Datasheet Preview
CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency • 36-Mbit Density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 450 MHz Clock for High Bandwidth • 2-word Burst for reducing Address Bus Frequency • Double Data Rate DDR Interfaces data transferred at 900 MHz at 450 MHz • Available in Clock Cycle Latency • Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only • Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems • Data Valid Pin QVLD to indicate Valid Data on the Output • Synchronous Internally Self Timed Writes • DDR II+ operates with Cycle Read Latency when DOFF is asserted HIGH • Operates similar to DDR I Device with 1 Cycle Read Latency when DOFF is asserted LOW • Core VDD = 1.8V ± 0.1V I/O VDDQ = 1.4V to VDD[1] Supports both 1.5V and 1.8V I/O supply • HSTL Inputs and Variable Drive HSTL Output Buffers • Available in 165-Ball FBGA Package 13 x 15 x mm • Offered in both Pb-free and non Pb-free Packages • JTAG Compatible Test Access Port • Phase Locked Loop PLL for Accurate Data Placement Configurations With Read Cycle Latency of cycles CY7C12461KV18 4M x 8 CY7C12571KV18 4M x 9 CY7C12481KV18 2M x 18 CY7C12501KV18 1M x 36 Functional Description The CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C12461KV18 , 9-bit words CY7C12571KV18 , 18-bit words CY7C12481KV18 , or 36-bit words CY7C12501KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. These devices are down bonded from the 65nm 72M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and the same JTAG ID code as the equivalent 72M device options. For details refer to the application note AN53189, 65nm Technology InterimQDRII+/DDRII+ SRAM device family description. Table Selection Guide 450 MHz Max Operating Frequency 450 Max Operating Current x8 630 x9 630 x18 650 x36 820 400 MHz 400 580 590 750 375 MHz 375 550 570 710 333 MHz 333 510 520 640 Unit MHz mA Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C12461KV18 CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 A 20:0 K DOFF VREF R/W NWS[1:0] Address Register CLK Gen. Control Logic Write Add. Decode Read Add. Decode Write Reg Write Reg 2M x 8 Array 2M x 8 Array Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 DC Electrical Characteristics 21 AC Electrical Characteristics 22 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence 25 Ordering Information 26 Ordering Code Definitions 26 Package Diagram 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29 Page 4 of 29 [+] Feedback CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 Pin Configuration The pin configuration for CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 follow.[2] 165-Ball FBGA 13 x 15 x mm Pinout CY7C12461KV18 4M x 8 CQ NC/72M NWS1 K NC/144M LD A NC/288M K NWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ QVLD CY7C12571KV18 4M x 9 CQ NC/72M K NC/144M LD A NC/288M K BWS0 VDDQ VDDQ VDDQ VDDQ Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 400 CY7C12481KV18-400BZC CY7C12501KV18-400BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Operating Range Commercial Ordering Code Definitions CY 7C12XXX K V18 - 400 BZ C Page 26 of 29 [+] Feedback CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 Package Diagram Figure 165-ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180 C Page 27 of 29 [+] Feedback CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 Document History Page Document Title 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency Document Number 001-53194 Orig. of Change Submission Date Description Of Change * 2702761 VKN/PYRS 05/06/2009 New Data Sheet A 2747707 VKN/AESA 08/03/2009 Converted from preliminary to final For 450 MHz speed, changed tCO, tCCQO, tCHZ from 370 ps to 450 ps and tDOH, tCQOH, tCLZ from -370 ps to -450 ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information B 2761928 09/10/2009 Post to external web C 2762555 09/11/2009 Updated Input and Output Capacitance. Modified Ordering code disclaimer. D 2868256 01/28/2010 Included CY7C12481KV18-400BZC in the Ordering Information table Updated 165-ball package diagram. E 2877876 02/12/2010 Included “CY7C12501KV18-450BZXC” part in the Ordering Information table. F 2890573 03/11/2010 Included “CY7C12481KV18-400BZXC” part in the Ordering Information table. G 2896003 03/19/2010 Removed CY7C12501KV18-450BZXC from the Ordering Information table. H 3056557 12/10/2010 Included CY7C12501KV18-450BZXC part to the Ordering Information table. Added Ordering Code Definition. *I 3158296 01/31/2011 Updated Ordering Information and added Ordering Code Definitions. Page 28 of 29 [+] Feedback CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 29 of 29 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency
36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency
• 36-Mbit Density 4M x 8, 4M x 9, 2M x 18, 1M x 36
• 450 MHz Clock for High Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate DDR Interfaces
data transferred at 900 MHz at 450 MHz
• Available in Clock Cycle Latency
• Two Input Clocks K and K for precise DDR Timing

SRAM uses rising edges only
• Echo Clocks CQ and CQ simplify Data Capture in High Speed

Systems
• Data Valid Pin QVLD to indicate Valid Data on the Output
• Synchronous Internally Self Timed Writes
• DDR II+ operates with Cycle Read Latency when DOFF is
asserted HIGH
• Operates similar to DDR I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
• Core VDD = 1.8V ± 0.1V I/O VDDQ = 1.4V to VDD[1]

Supports both 1.5V and 1.8V I/O supply
• HSTL Inputs and Variable Drive HSTL Output Buffers
• Available in 165-Ball FBGA Package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free Packages
• JTAG Compatible Test Access Port
• Phase Locked Loop PLL for Accurate Data Placement

Configurations

With Read Cycle Latency of cycles CY7C12461KV18 4M x 8 CY7C12571KV18 4M x 9 CY7C12481KV18 2M x 18 CY7C12501KV18 1M x 36

Functional Description

The CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C12461KV18 , 9-bit words CY7C12571KV18 , 18-bit words CY7C12481KV18 , or 36-bit words CY7C12501KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. These devices are down bonded from the 65nm 72M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and the same JTAG ID code as the equivalent 72M device options. For details refer to the application note AN53189, 65nm Technology InterimQDRII+/DDRII+ SRAM device family description.

Table Selection Guide
450 MHz

Max Operating Frequency 450

Max Operating Current x8 630
x9 630
x18 650
x36 820
400 MHz 400 580 590 750
375 MHz 375 550 570 710
333 MHz 333 510 520 640

Unit

MHz mA

Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C12461KV18

CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18

A 20:0

K DOFF

VREF R/W NWS[1:0]

Address Register

CLK Gen.

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg
2M x 8 Array 2M x 8 Array
Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 DC Electrical Characteristics 21 AC Electrical Characteristics 22 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence 25 Ordering Information 26 Ordering Code Definitions 26 Package Diagram 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29

Page 4 of 29 [+] Feedback

CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18

Pin Configuration

The pin configuration for CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 follow.[2]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C12461KV18 4M x 8

CQ NC/72M

NWS1

K NC/144M LD

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

QVLD

CY7C12571KV18 4M x 9

CQ NC/72M

K NC/144M LD

A NC/288M K

BWS0

VDDQ

VDDQ

VDDQ

VDDQ
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
400 CY7C12481KV18-400BZC

CY7C12501KV18-400BZC

Package Diagram

Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial
Ordering Code Definitions CY 7C12XXX K V18 - 400 BZ C

Page 26 of 29 [+] Feedback

CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18

Package Diagram

Figure 165-ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180 *C

Page 27 of 29 [+] Feedback

CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18

Document History Page

Document Title 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency Document Number 001-53194

Orig. of Change

Submission Date

Description Of Change
** 2702761 VKN/PYRS 05/06/2009 New Data Sheet
*A 2747707 VKN/AESA 08/03/2009 Converted from preliminary to final For 450 MHz speed, changed tCO, tCCQO, tCHZ from 370 ps to 450 ps and tDOH, tCQOH, tCLZ from -370 ps to -450 ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information
*B 2761928
09/10/2009 Post to external web
*C 2762555
09/11/2009 Updated Input and Output Capacitance. Modified Ordering code disclaimer.
*D 2868256
01/28/2010 Included CY7C12481KV18-400BZC in the Ordering Information table Updated 165-ball package diagram.
*E 2877876
02/12/2010 Included “CY7C12501KV18-450BZXC” part in the Ordering Information table.
*F 2890573
03/11/2010 Included “CY7C12481KV18-400BZXC” part in the Ordering Information table.
*G 2896003
03/19/2010 Removed CY7C12501KV18-450BZXC from the Ordering Information table.
*H 3056557
12/10/2010 Included CY7C12501KV18-450BZXC part to the Ordering Information table. Added Ordering Code Definition.
*I 3158296
01/31/2011 Updated Ordering Information and added Ordering Code Definitions.

Page 28 of 29 [+] Feedback

CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 29 of 29

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C12481KV18-400BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C12481KV18-400BZXC 507932