CY7C1231H-133AXC

CY7C1231H-133AXC Datasheet

CY7C1231H

Part	Datasheet
CY7C1231H-133AXC	CY7C1231H-133AXC (pdf)

PDF Datasheet Preview
CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture • Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 128K x 18 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times ns 133-MHz device • Clock Enable CEN pin to suspend operation • Synchronous self-timed write • Asynchronous Output Enable • Offered in JEDEC-standard lead-free 100-pin TQFP package • Burst or interleaved burst order • Low standby power Functional Description[1] The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231H is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device . Write operations are controlled by the two Byte Write Select BW[A:B] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Logic Block Diagram A0, A1, A MODE ADDRESS REGISTER A1 A0 D1 D0 ADV/LD C WRITE ADDRESS REGISTER Q1 A1' Q0 A0' BURST LOGIC ADV/LD BWA BWB WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY WRITE ARRAY DRIVERS OE CE1 CE2 CE3 READ LOGIC SLEEP CONTROL INPUT E REGISTER Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on DQs DQPA DQPB Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Pin Configuration 133 MHz 225 40 100-pin TQFP Pinout Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered”. Speed MHz Ordering Code Package Diagram Package Type Operating Range 133 CY7C1231H-133AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1231H-133AXI 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial Package Diagram 100-pin TQFP 14 x 20 x mm 51-85050 100 1 81 80 R MIN. MAX. GAUGE PLANE 0° -7° REF. 30 31 0° MIN. R MIN. MAX. MIN. DETAIL A TYP. 51 50 12° ±1° 8X SEE DETAIL MAX. MAX. STAND-OFF MIN. MAX. SEATING PLANE NOTE JEDEC STD REF MS-026 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED in mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH DIMENSIONS IN MILLIMETERS 51-85050-B NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders. Page 11 of 12 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1231H Document History Page Document Title CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Document Number 001-00207 Orig. of ECN NO. Issue Date Change Description of Change 347377 See ECN PCI New Data Sheet 428408 See ECN NXR Converted from Preliminary to Final. Modified test condition from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table. Updated the Ordering Information Table. Replaced Package Diagram of 51-85050 from A to *B 459347 See ECN NXR Included 2.5V I/O option Updated the Ordering Information table. Page 12 of 12

PDF Datasheet Preview

CY7C1231H
2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture
• Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 128K x 18 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
ns 133-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed write
• Asynchronous Output Enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• Burst or interleaved burst order
• Low standby power

Functional Description[1]

The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231H is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device .

Write operations are controlled by the two Byte Write Select BW[A:B] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

MODE

ADDRESS REGISTER

A1 A0

D1 D0

ADV/LD C

WRITE ADDRESS REGISTER

Q1 A1' Q0 A0' BURST LOGIC

ADV/LD BWA BWB

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

MEMORY

WRITE

ARRAY

DRIVERS

OE CE1 CE2 CE3

READ LOGIC

SLEEP CONTROL

INPUT E REGISTER

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on

DQs DQPA DQPB

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current

Pin Configuration
133 MHz 225 40
100-pin TQFP Pinout
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered”.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
133 CY7C1231H-133AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1231H-133AXI 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Industrial

Package Diagram
100-pin TQFP 14 x 20 x mm 51-85050
100 1
81 80

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
30 31
0° MIN.

R MIN. MAX.

MIN.

DETAIL A

TYP.
51 50
12° ±1° 8X

SEE DETAIL

MAX. MAX.

STAND-OFF MIN. MAX.

SEATING PLANE NOTE JEDEC STD REF MS-026 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED in mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH DIMENSIONS IN MILLIMETERS
51-85050-*B

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 11 of 12

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C1231H

Document History Page

Document Title CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Document Number 001-00207

Orig. of ECN NO. Issue Date Change

Description of Change
347377 See ECN

PCI New Data Sheet
428408 See ECN NXR Converted from Preliminary to Final.
Modified test condition from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering

Information table.
Updated the Ordering Information Table.

Replaced Package Diagram of 51-85050 from *A to *B
459347 See ECN NXR Included 2.5V I/O option
Updated the Ordering Information table.

Page 12 of 12

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1231H-133AXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1231H-133AXC 507930