CY7C1062AV33-10BGIT

CY7C1062AV33-10BGIT Datasheet

CY7C1062AV33

Part	Datasheet
CY7C1062AV33-10BGIT	CY7C1062AV33-10BGIT (pdf)

Related Parts	Information
CY7C1062AV33-10BGCT	CY7C1062AV33-10BGCT
CY7C1062AV33-10BGI	CY7C1062AV33-10BGI
CY7C1062AV33-10BGC	CY7C1062AV33-10BGC

PDF Datasheet Preview
CY7C1062AV33 512K x 32 Static RAM • High speed tAA = 8 ns • Low active power 1080 mW max. • Operating voltages of ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and CE3 features • Available in non Pb-free 119-ball PBGA package Functional Description The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. Writing to the device is accomplished by enabling the chip CE1, CE2, and CE3 LOW and forcing the Write Enable WE input LOW. If Byte Enable A BA is LOW, then data from I/O Logic Block Diagram INPUT BUFFERS A3 A4 512K x 32 ARRAY A7 A8 A9 pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A18 . If Byte Enable B BB is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A18 . Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23 and I/O24 to I/O31, respectively. Reading from the device is accomplished by enabling the chip CE1, CE2, and CE3 LOW while forcing the Output Enable OE LOW and Write Enable WE HIGH. If the first Byte Enable BA is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte Enable B BB is LOW, then data from memory will appear on I/O8 to I/O15. Similarly, Bc and BD correspond to the third and fourth bytes. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins I/O0 through I/O31 are placed in a high-impedance state when the device is deselected CE1, CE2or CE3 HIGH , the outputs are disabled OE HIGH , the byte selects are disabled BA-D HIGH , or during a write operation CE1, CE2, and CE3 LOW, and WE LOW . The CY7C1062AV33 is available in a 119-ball pitch ball grid array PBGA package. WE CE1 CE2 CE3 OE BA BB BC BD COLUMN DECODER ROW DECODER A15 AA1176 A18 SENSE AMPS OUTPUT BUFFERS CONTROL LOGIC Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Unit Com’l Ind’l Com’l/Ind’l Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Pin Configurations[1, 2] I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 Ordering Information Speed ns 8 10 Ordering Code CY7C1062AV33-8BGC CY7C1062AV33-10BGC CY7C1062AV33-10BGI CY7C1062AV33-12BGC CY7C1062AV33-12BGI Package Diagram Package Name 51-85115 Package Type 119-ball 14 x 22 x mm PBGA 119-ball PBGA 14 x 22 x mm 51-85115 CY7C1062AV33 Operating Range Commercial Industrial Commercial Industrial 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Page 8 of 9 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1062AV33 Document History Page Document Title CY7C1062AV33 512K x 32 Static RAM Document Number 38-05137 Orig. of ECN NO. Issue Date Change Description of Change 109752 02/27/02 HGK New Data Sheet 117059 09/19/02 DFP Removed 15-ns bin and added 8-ns bin. Changed CE2 TO CE2. Changed CIN input capacitance from 6 pF to 8 pF. Changed COUT output capacitance from 8 pF to 10 pF. 119389 10/07/02 DFP Updated ICC, Tsd, and Tdoe parameters. Removed note 7 IZ/hZ comment . 120384 11/13/02 DFP Final Data Sheet. Removed note Added note 3 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd. 124440 2/25/03 MEG Changed ISB1 from 100 mA to 70 mA 329638 See ECN RKF Removed CE2 waveform showing Active High signal timing on Page #5, and included it with the CE1, CE3 waveform Corrected Truth Table on page 7 with CE2 active low information 492137 See ECN NXR Included note #1 and 2 on page #2 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated Ordering Information Table Page 9 of 9

PDF Datasheet Preview

CY7C1062AV33
512K x 32 Static RAM
• High speed tAA = 8 ns
• Low active power 1080 mW max.
• Operating voltages of ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and CE3
features
• Available in non Pb-free 119-ball PBGA package

Functional Description

The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. Writing to the device is accomplished by enabling the chip CE1, CE2, and CE3 LOW and forcing the Write Enable WE input LOW. If Byte Enable A BA is LOW, then data from I/O

Logic Block Diagram

INPUT BUFFERS

A3 A4
512K x 32 ARRAY

A7 A8 A9
pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A18 . If Byte Enable B BB is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A18 . Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23 and I/O24 to I/O31, respectively. Reading from the device is accomplished by enabling the chip CE1, CE2, and CE3 LOW while forcing the Output Enable OE LOW and Write Enable WE HIGH. If the first Byte Enable BA is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte Enable B BB is LOW, then data from memory will appear on I/O8 to I/O15. Similarly, Bc and BD correspond to the third and fourth bytes. See the truth table at the back of this data sheet for a complete description of read and write modes.

The input/output pins I/O0 through I/O31 are placed in a high-impedance state when the device is deselected CE1, CE2or CE3 HIGH , the outputs are disabled OE HIGH , the byte selects are disabled BA-D HIGH , or during a write operation CE1, CE2, and CE3 LOW, and WE LOW . The CY7C1062AV33 is available in a 119-ball pitch ball grid array PBGA package.

WE CE1 CE2 CE3 OE BA BB BC BD

COLUMN DECODER

ROW DECODER A15 AA1176 A18

SENSE AMPS OUTPUT BUFFERS

CONTROL LOGIC

Selection Guide

Maximum Access Time Maximum Operating Current

Maximum CMOS Standby Current

Unit

Com’l

Ind’l

Com’l/Ind’l

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

Pin Configurations[1, 2]

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

I/O24

I/O25

I/O26

I/O27
Ordering Information

Speed ns 8 10
Ordering Code CY7C1062AV33-8BGC CY7C1062AV33-10BGC CY7C1062AV33-10BGI CY7C1062AV33-12BGC CY7C1062AV33-12BGI

Package Diagram

Package Name
51-85115

Package Type 119-ball 14 x 22 x mm PBGA
119-ball PBGA 14 x 22 x mm 51-85115

CY7C1062AV33

Operating Range

Commercial

Industrial Commercial

Industrial
51-85115-*B

All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 8 of 9

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C1062AV33

Document History Page

Document Title CY7C1062AV33 512K x 32 Static RAM Document Number 38-05137

Orig. of ECN NO. Issue Date Change

Description of Change
109752 02/27/02

HGK New Data Sheet
117059 09/19/02

DFP Removed 15-ns bin and added 8-ns bin.

Changed CE2 TO CE2. Changed CIN input capacitance from 6 pF to 8 pF. Changed COUT output capacitance from 8 pF to 10 pF.
119389 10/07/02

DFP Updated ICC, Tsd, and Tdoe parameters.

Removed note 7 IZ/hZ comment .
120384 11/13/02

DFP Final Data Sheet.

Removed note

Added note 3 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd.
124440 2/25/03

MEG Changed ISB1 from 100 mA to 70 mA
329638 See ECN

RKF Removed CE2 waveform showing Active High signal timing on Page #5, and
included it with the CE1, CE3 waveform

Corrected Truth Table on page 7 with CE2 active low information
492137 See ECN NXR Included note #1 and 2 on page #2

Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table
Updated Ordering Information Table

Page 9 of 9

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1062AV33-10BGIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1062AV33-10BGIT 507912