CY7C1061AV33-12ZXIT

CY7C1061AV33-12ZXIT Datasheet

CY7C1061AV33

Part	Datasheet
CY7C1061AV33-12ZXIT	CY7C1061AV33-12ZXIT (pdf)

Related Parts	Information
CY7C1061AV33-10BAC	CY7C1061AV33-10BAC
CY7C1061AV33-12ZXCT	CY7C1061AV33-12ZXCT
CY7C1061AV33-12ZXI	CY7C1061AV33-12ZXI
CY7C1061AV33-12ZXC	CY7C1061AV33-12ZXC

PDF Datasheet Preview
CY7C1061AV33 16-Mbit 1M x 16 Static RAM • High speed tAA = 10 ns • Low active power 990 mW max • Operating voltages of ± 0.3V • 2.0V data retention • Automatic power down when deselected • TTL compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features • Available in Pb-free and non Pb-free 54-pin TSOP II package and non Pb-free 60-ball fine pitch ball grid array FBGA package Logic Block Diagram Functional Description The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, enable the chip CE1 LOW and CE2 HIGH while forcing the Write Enable WE input LOW. If Byte Low Enable BLE is LOW, then data from IO pins IO0 through IO7 , is written into the location specified on the address pins A0 through A19 . If Byte High Enable BHE is LOW, then data from IO pins IO8 through IO15 is written into the location specified on the address pins A0 through A19 . To read from the device, enable the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable OE LOW and the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on IO0 to IO7. If Byte High Enable BHE is LOW, then data from memory will appear on IO8 to IO15. See “Truth Table” on page 7 for a complete description of Read and Write modes. The input/output pins IO0 through IO15 are placed in a high-impedance state when the device is deselected CE1 HIGH/CE2 LOW , the outputs are disabled OE HIGH , the BHE and BLE are disabled BHE, BLE HIGH , or a Write operation is in progress CE1 LOW, CE2 HIGH, and WE LOW . ROW DECODER SENSE AMPS INPUT BUFFER A3 A4 A5 1M x 16 ARRAY A7 A8 A9 COLUMN DECODER 13 14 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1061AV33 Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/Industrial Pin Configurations [1, 2] 60-ball FBGA Top View BLE OE A0 A1 A2 CE2 IO 8 BHE A3 A4 CE1 IO 0 IO 9 IO 10 A5 A6 IO 1 IO 2 VSS IO11 A17 A7 IO 3 VCC VCC IO 12 NC A16 IO 4 VSS IO 14 IO 13 A14 A15 IO 5 IO 6 IO 15 DNU A12 A13 WE IO 7 A18 A8 A10 A11 Ordering Information Speed ns Ordering Code Package Diagram CY7C1061AV33-10ZXC 51-85160 CY7C1061AV33-10BAC 51-85162 CY7C1061AV33-10ZI 51-85160 CY7C1061AV33-10ZXI CY7C1061AV33-10BAXI 51-85162 CY7C1061AV33-12ZC 51-85160 CY7C1061AV33-12ZXC CY7C1061AV33-12BAC 51-85162 CY7C1061AV33-12ZXI 51-85160 Contact local Cypress representative for availability of the these parts. Package Type 54-pin TSOP II Pb-free 60-ball FBGA 54-pin TSOP II 54-pin TSOP II Pb-free 60-ball FBGA Pb-free 54-pin TSOP II 54-pin TSOP II Pb-free 60-ball FBGA 54-pin TSOP II Pb-free Package Diagrams Figure 54-pin TSOP II, 51-85160 CY7C1061AV33 Operating Range Commercial Industrial Commercial Industrial 51-85160-** Page 8 of 10 [+] Feedback CY7C1061AV33 Package Diagrams continued Figure 60-ball FBGA 8 x 20 x mm , 51-85162 A1 CORNER TOP VIEW 12 3 4 5 6 A B C D E F G H BOTTOM VIEW 65 4321 A1 CORNER DUMMY BALL X12 M C M C A B Ø0.30±0.05 48X A B C D E F G H DIMENSIONS IN MM SEATING PLANE C B 0.15 4X PART # Shaded fBGA production ordering information 492137 See ECN NXR Corrected Block Diagram on page #1 Removed 8 ns speed bin Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration Included Note #1 and 2 on page #2 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table 508117 See ECN NXR Updated FBGA Pin Configuration Updated Ordering Information table 877322 See ECN VKN Updated Ordering Information table Page 10 of 10 [+] Feedback

PDF Datasheet Preview

CY7C1061AV33
16-Mbit 1M x 16 Static RAM
• High speed tAA = 10 ns
• Low active power 990 mW max
• Operating voltages of ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free and non Pb-free 54-pin TSOP II
package and non Pb-free 60-ball fine pitch ball grid array FBGA package

Logic Block Diagram

Functional Description

The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits.

To write to the device, enable the chip CE1 LOW and CE2 HIGH while forcing the Write Enable WE input LOW. If Byte Low Enable BLE is LOW, then data from IO pins IO0 through IO7 , is written into the location specified on the address pins A0 through A19 . If Byte High Enable BHE is LOW, then data from IO pins IO8 through IO15 is written into the location specified on the address pins A0 through A19 .

To read from the device, enable the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable OE LOW and the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on IO0 to IO7. If Byte High Enable BHE is LOW, then data from memory will appear on IO8 to IO15. See “Truth Table” on page 7 for a complete description of Read and Write modes.

The input/output pins IO0 through IO15 are placed in a high-impedance state when the device is deselected CE1 HIGH/CE2 LOW , the outputs are disabled OE HIGH , the BHE and BLE are disabled BHE, BLE HIGH , or a Write operation is in progress CE1 LOW, CE2 HIGH, and WE LOW .

ROW DECODER SENSE AMPS

INPUT BUFFER

A3 A4 A5
1M x 16 ARRAY

A7 A8 A9

COLUMN DECODER
13 14
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1061AV33

Selection Guide

Maximum Access Time Maximum Operating Current

Maximum CMOS Standby Current

Commercial

Industrial

Commercial/Industrial

Pin Configurations [1, 2]
60-ball FBGA Top View

BLE OE A0 A1 A2 CE2

IO 8 BHE A3 A4 CE1 IO 0

IO 9 IO 10 A5

A6 IO 1 IO 2

VSS IO11 A17 A7

IO 3 VCC

VCC IO 12 NC A16 IO 4 VSS

IO 14 IO 13 A14 A15 IO 5 IO 6

IO 15 DNU A12 A13 WE IO 7

A18 A8

A10 A11
Ordering Information

Speed ns
Ordering Code

Package Diagram

CY7C1061AV33-10ZXC
51-85160

CY7C1061AV33-10BAC
51-85162

CY7C1061AV33-10ZI
51-85160

CY7C1061AV33-10ZXI

CY7C1061AV33-10BAXI
51-85162

CY7C1061AV33-12ZC
51-85160

CY7C1061AV33-12ZXC

CY7C1061AV33-12BAC
51-85162

CY7C1061AV33-12ZXI
51-85160

Contact local Cypress representative for availability of the these parts.

Package Type
54-pin TSOP II Pb-free 60-ball FBGA 54-pin TSOP II 54-pin TSOP II Pb-free 60-ball FBGA Pb-free 54-pin TSOP II 54-pin TSOP II Pb-free 60-ball FBGA 54-pin TSOP II Pb-free

Package Diagrams

Figure 54-pin TSOP II, 51-85160

CY7C1061AV33

Operating Range Commercial Industrial Commercial Industrial
51-85160-**

Page 8 of 10 [+] Feedback

CY7C1061AV33

Package Diagrams continued

Figure 60-ball FBGA 8 x 20 x mm , 51-85162

A1 CORNER

TOP VIEW 12 3 4 5 6

A B C D E F G H

BOTTOM VIEW 65 4321

A1 CORNER DUMMY BALL X12

M C M C A B Ø0.30±0.05 48X

A B C D E F G H

DIMENSIONS IN MM

SEATING PLANE C

B 0.15 4X

PART #
Shaded fBGA production ordering information
492137 See ECN NXR Corrected Block Diagram on page #1

Removed 8 ns speed bin

Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration

Included Note #1 and 2 on page #2

Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table
Updated the Ordering Information Table
508117 See ECN NXR Updated FBGA Pin Configuration
Updated Ordering Information table
877322 See ECN
VKN Updated Ordering Information table

Page 10 of 10 [+] Feedback

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Datasheet ID: CY7C1061AV33-12ZXIT 507910