CY7C1020B
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CY7C1020B-12VXCT (pdf) |
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CY7C1020B-12ZXC |
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CY7C1020B-12ZXCT |
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CY7C1020B-15ZXCT |
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CY7C1020B-12VXC |
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CY7C1020B 32K x 16 Static RAM ROW DECODER A8 A9 A10 A11 A12 A13 A14 SENSE AMPS • High speed tAA = 12, 15 ns • CMOS for optimum speed/power • Low active power 825 mW max. • Low CMOS standby power mW max. • Automatic power-down when deselected • Independent control of upper and lower bits • Available in lead-free and non-lead-free 44-pin TSOP II and 44-pin 400-mil SOJ packages Functional Description The CY7C1020B is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Logic Block Diagram DATA IN DRIVERS 32K x 16 RAM Array COLUMN DECODER Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O1 through I/O8 , is written into the location specified on the address pins A0 through A14 . If Byte High Enable BHE is LOW, then data from I/O pins I/O9 through I/O16 is written into the location specified on the address pins A0 through A14 . Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable BHE is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins I/O1 through I/O16 are placed in a high-impedance state when the device is deselected CE HIGH , the outputs are disabled OE HIGH , the BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE LOW, and WE LOW . The CY7C1020B is available in standard 44-pin TSOP Type II and 44-pin 400-mil-wide SOJ packages. BHE WE CE OE BLE Pin Configuration SOJ / TSOP II Pinout Top View A3 2 A2 3 A1 4 A0 5 CE 6 I/O1 7 I/O2 8 I/O3 9 I/O4 10 VCC 11 VSS 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 WE 17 A4 18 A14 19 A13 20 A12 21 NC 22 44 A5 43 A6 42 A7 41 OE 40 BHE 39 BLE 38 I/O16 37 I/O15 36 I/O14 35 I/O13 34 VSS 33 VCC 32 I/O12 31 I/O11 30 I/O10 29 I/O9 28 NC 27 A8 26 A9 25 A10 24 A11 23 NC Selection Guide Maximum Access Time ns Maximum Operating Current mA Maximum CMOS Standby Current mA CY7C1020B-12 140 3 CY7C1020B-15 130 3 Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1020B Maximum Ratings Above which the useful life may be impaired. For user guidelines, not tested. Storage Temperature to +150°C Current into Outputs 20 mA Static Discharge >2001V per MIL-STD-883, Method 3015 Ordering Information Speed ns 12 Ordering Code CY7C1020B-12VC CY7C1020B-12VXC CY7C1020B-12ZC CY7C1020B-12ZXC CY7C1020B-15ZC CY7C1020B-15ZXC Package Diagrams Package Diagram 51-85082 51-85087 51-85087 Package Type 44-pin 400-Mil Molded SOJ 44-pin 400-Mil Molded SOJ Pb-free 44-pin TSOP Type II 44-pin TSOP Type II Pb-free 44-pin TSOP Type II 44-pin TSOP Type II Pb-free 44-pin 400-Mil Molded SOJ 51-85082 CY7C1020B Operating Range Commercial 51-85082-*B Page 7 of 9 [+] Feedback Package Diagrams continued 44-pin TSOP II 51-85087 CY7C1020B 51-85087-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Page 8 of 9 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1020B Document History Page Document Title CY7C1020B 32K x 16 Static RAM Document # 38-05171 Issue ECN NO. Date Orig. of Change Description of Change 115439 05/09/02 DSG New Data Sheet 116869 08/21/02 DFP Added L-Power Specifications. 426747 See ECN ZSD Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court”. Added thermal resistance table. Updated the ordering information table and replaced the Package Name column with Package Diagram. 465909 See ECN NXR Corrected typo in Pin Configuration Changed A15 to A4 Removed L-Power Specifications Updated the Ordering Information table Page 9 of 9 [+] Feedback |
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