CY7C019V-20AXI

CY7C019V-20AXI Datasheet

CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM

Part	Datasheet
CY7C019V-20AXI	CY7C019V-20AXI (pdf)

Related Parts	Information
CY7C019V-15AXC	CY7C019V-15AXC
CY7C008V-25AXC	CY7C008V-25AXC
CY7C019V-25AXC	CY7C019V-25AXC
CY7C019V-15AC	CY7C019V-15AC
CY7C019V-20AXC	CY7C019V-20AXC

PDF Datasheet Preview
CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 64K x 8 organization CY7C008 • 128K x 8 organization CY7C009 • 64K x 9 organization CY7C018 • 128K x 9 organization CY7C019 • 0.35-micron CMOS for optimum speed/power • High-speed access 15/20/25 ns • Low operating power Active ICC = 115 mA typical Standby ISB3 = 10 µA typical • Fully asynchronous operation Logic Block Diagram R/WL CE0L CE1L CY7C008V/009V CY7C018V/019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Dual Chip Enables • Pin select for Master or Slave • Commercial and Industrial Temperature Ranges • Available in 100-pin TQFP • Pb-Free packages available R/WR CE0R CE1R I/O Control I/O Control 16/17 Address Decode True Dual-Ported RAM Array CEL OEL R/WL SEML BUSYL [3] INTL 16/17 for x8 devices for x9 devices. for 64K devices for 128K. BUSY is an output in master mode and an input in slave mode. Interrupt Semaphore Arbitration Address Decode 16/17 16/17 CER OER R/WR SEMR [3] BUSYR INTR Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C008V/009V CY7C018V/019V Functional Description The CY7C008V/009V and CY7018V/019V are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select CE pin. The CY7C008V/009V and CY7018V/019V are available in 100-pin Thin Quad Plastic Flatpacks TQFP . Pin Configurations 100-Pin TQFP Top View NC A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L [4] A16L VCC NC CE0L CE1L SEML R/WL OEL GND NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Ordering Information 64K x8 3.3V Asynchronous Dual-Port SRAM Speed ns Ordering Code CY7C008V-15AC CY7C008V-20AC CY7C008V-25AC CY7C008V-25AXC Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial 64K x9 3.3V Asynchronous Dual-Port SRAM Speed ns Ordering Code CY7C018V-15AC CY7C018V-20AC CY7C018V-25AC Package Name A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Commercial 128K x8 3.3V Asynchronous Dual-Port SRAM Speed ns 15 Ordering Code CY7C009V-15AC CY7C009V-15AXC CY7C009V-20AC CY7C009V-20AI CY7C009V-20AXI CY7C009V-25AC CY7C009V-25AXC Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Industrial Commercial 128K x9 3.3V Asynchronous Dual-Port SRAM Speed ns 15 20 Ordering Code CY7C019V-15AC CY7C019V-15AXC CY7C019V-20AC CY7C019V-20AXC CY7C019V-20AI CY7C019V-20AXI CY7C019V-25AC CY7C019V-25AXC Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Industrial Commercial Page 16 of 18 [+] Feedback Package Diagram CY7C008V/009V CY7C018V/019V 100-Pin Thin Plastic Quad Flat Pack TQFP A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack TQFP A100 51-85048-*B All products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 18 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C008V/009V CY7C018V/019V Document History Page Document Title CY7C008V/009V, CY7C018V/019V 3.3V 64K/128K X 8/9 Dual Port Static RAM Document Number 38-06044 Issue ECN NO. Date Orig. of Change Description of Change 110192 09/29/01 SZV Change from Spec number 38-00669 to 38-06044 113541 04/15/02 OOR Change pin 85 from BUSYL to BUSYR pg. 3 122294 12/27/02 RBI Power up requirements added to Maximum Ratings Information 393440 See ECN YIM Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C008V-25AXC, CY7C009V-15AXC, CY7C009V-20AXI, CY7C009V-25AXC, CY7C019V-15AXC, CY7C019V-20AXC, CY7C019V-20AXI, CY7C019V-25AXC Page 18 of 18 [+] Feedback

PDF Datasheet Preview

CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 64K x 8 organization CY7C008
• 128K x 8 organization CY7C009
• 64K x 9 organization CY7C018
• 128K x 9 organization CY7C019
• 0.35-micron CMOS for optimum speed/power
• High-speed access 15/20/25 ns
• Low operating power

Active ICC = 115 mA typical Standby ISB3 = 10 µA typical
• Fully asynchronous operation

Logic Block Diagram

R/WL

CE0L CE1L

CY7C008V/009V CY7C018V/019V
3.3V 64K/128K x 8/9 Dual-Port Static RAM
• Automatic power-down
• Expandable data bus to 16/18 bits or more using

Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 100-pin TQFP
• Pb-Free packages available

R/WR CE0R CE1R

I/O Control

I/O Control
16/17

Address Decode

True Dual-Ported RAM Array

CEL OEL

R/WL SEML BUSYL [3] INTL
16/17
for x8 devices for x9 devices. for 64K devices for 128K. BUSY is an output in master mode and an input in slave mode.

Interrupt Semaphore Arbitration

Address Decode
16/17
16/17

CER OER

R/WR SEMR [3] BUSYR

INTR

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C008V/009V CY7C018V/019V

Functional Description

The CY7C008V/009V and CY7018V/019V are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select CE pin.

The CY7C008V/009V and CY7018V/019V are available in 100-pin Thin Quad Plastic Flatpacks TQFP .

Pin Configurations
100-Pin TQFP Top View

NC A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R NC

NC A7L A8L A9L A10L A11L A12L A13L A14L A15L [4] A16L VCC NC CE0L CE1L SEML R/WL OEL GND NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Ordering Information
64K x8 3.3V Asynchronous Dual-Port SRAM

Speed ns
Ordering Code CY7C008V-15AC CY7C008V-20AC CY7C008V-25AC CY7C008V-25AXC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack

Operating Range

Commercial

Commercial

Commercial
64K x9 3.3V Asynchronous Dual-Port SRAM

Speed ns
Ordering Code CY7C018V-15AC CY7C018V-20AC CY7C018V-25AC

Package Name

A100

A100

A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack

Operating Range

Commercial

Commercial

Commercial
128K x8 3.3V Asynchronous Dual-Port SRAM

Speed ns 15
Ordering Code CY7C009V-15AC CY7C009V-15AXC CY7C009V-20AC CY7C009V-20AI CY7C009V-20AXI CY7C009V-25AC CY7C009V-25AXC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack

Operating Range

Commercial

Commercial Industrial

Commercial
128K x9 3.3V Asynchronous Dual-Port SRAM

Speed ns 15 20
Ordering Code CY7C019V-15AC CY7C019V-15AXC CY7C019V-20AC CY7C019V-20AXC CY7C019V-20AI CY7C019V-20AXI CY7C019V-25AC CY7C019V-25AXC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack

Operating Range

Commercial

Commercial

Industrial

Commercial

Page 16 of 18 [+] Feedback

Package Diagram

CY7C008V/009V CY7C018V/019V
100-Pin Thin Plastic Quad Flat Pack TQFP A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack TQFP A100
51-85048-*B

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 17 of 18

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY7C008V/009V CY7C018V/019V

Document History Page

Document Title CY7C008V/009V, CY7C018V/019V 3.3V 64K/128K X 8/9 Dual Port Static RAM Document Number 38-06044

Issue ECN NO. Date

Orig. of Change Description of Change
110192 09/29/01 SZV

Change from Spec number 38-00669 to 38-06044
113541 04/15/02 OOR

Change pin 85 from BUSYL to BUSYR pg. 3
122294 12/27/02 RBI

Power up requirements added to Maximum Ratings Information
393440 See ECN YIM

Added Pb-Free Logo
Added Pb-Free parts to ordering information:

CY7C008V-25AXC, CY7C009V-15AXC, CY7C009V-20AXI,

CY7C009V-25AXC, CY7C019V-15AXC, CY7C019V-20AXC,

CY7C019V-20AXI, CY7C019V-25AXC

Page 18 of 18 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C019V-20AXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C019V-20AXI 507881