74ABT373CMSA

74ABT373CMSA Datasheet

74ABT373 Octal Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ABT373CMSA	74ABT373CMSA (pdf)

Related Parts	Information
74ABT373CMTC	74ABT373CMTC
74ABT373CPC	74ABT373CPC
74ABT373CMSAX	74ABT373CMSAX
74ABT373CSCX	74ABT373CSCX
74ABT373CMTCX	74ABT373CMTCX
74ABT373CSC	74ABT373CSC
74ABT373CSJ	74ABT373CSJ
74ABT373CSJX	74ABT373CSJX

PDF Datasheet Preview
74ABT373 Octal Transparent Latch with 3-STATE Outputs 74ABT373 Octal Transparent Latch with 3-STATE Outputs March 2007 • 3-STATE outputs for bus interfacing • Output sink capability of 64mA, source capability of 32mA • Guaranteed output skew • Guaranteed multiple output switching specifications • Output switching specified for both 50pF and 250pF loads • Guaranteed simultaneous switching, noise level and dynamic threshold performance • Guaranteed latchup protection • High-impedance, glitch-free bus loading during entire power up and power down • Nondestructive, hot-insertion capability The ABT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state. Ordering Information Package Order Number Package Description 74ABT373CSC 74ABT373CSJ 74ABT373CMSA M20B M20D MSA20 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide 74ABT373CMTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names Data Inputs Latch Enable Input Active HIGH Output Enable Input Active LOW 3-STATE Latch Outputs 74ABT373 Octal Transparent Latch with 3-STATE Outputs Functional Description The ABT373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance State Logic Diagram Output On H L On no change Z Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1993 Fairchild Semiconductor Corporation 74ABT373 Octal Transparent Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TSTG TA TJ VCC VIN IIN VO Parameter Storage Temperature Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage 1 Input Current 1 Voltage Applied to Any Output Disabled or Power-Off State HIGH State Current Applied to Output in LOW State Max. DC Latchup Source Current Across Common Operating Range OE Pin Other Pins Over Voltage Latchup I/O Rating to +150°C to +125°C to +150°C to +7.0V to +7.0V to +5.0mA to +5.5V to VCC twice the rated IOL mA Note Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. TA VCC / Parameter Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate Data Input Enable Input Rating to +85°C +4.5V to +5.5V 50mV/ns 20mV/ns 1993 Fairchild Semiconductor Corporation 74ABT373 Octal Transparent Latch with 3-STATE Outputs DC Electrical Characteristics Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current

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74ABT373 Octal Transparent Latch with 3-STATE Outputs
74ABT373 Octal Transparent Latch with 3-STATE Outputs

March 2007
• 3-STATE outputs for bus interfacing
• Output sink capability of 64mA, source capability of
32mA
• Guaranteed output skew
• Guaranteed multiple output switching specifications
• Output switching specified for both 50pF and 250pF
loads
• Guaranteed simultaneous switching, noise level and
dynamic threshold performance
• Guaranteed latchup protection
• High-impedance, glitch-free bus loading during entire
power up and power down
• Nondestructive, hot-insertion capability

The ABT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state.
Ordering Information

Package Order Number

Package Description
74ABT373CSC 74ABT373CSJ 74ABT373CMSA

M20B M20D MSA20
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide
74ABT373CMTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Descriptions

Pin Names

Data Inputs Latch Enable Input Active HIGH

Output Enable Input Active LOW
3-STATE Latch Outputs
74ABT373 Octal Transparent Latch with 3-STATE Outputs

Functional Description

The ABT373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance State

Logic Diagram

Output On H L

On no change Z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1993 Fairchild Semiconductor Corporation
74ABT373 Octal Transparent Latch with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

TSTG TA TJ VCC VIN IIN VO

Parameter Storage Temperature Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage 1 Input Current 1 Voltage Applied to Any Output

Disabled or Power-Off State HIGH State Current Applied to Output in LOW State Max. DC Latchup Source Current Across Common Operating Range OE Pin Other Pins Over Voltage Latchup I/O

Rating to +150°C to +125°C to +150°C to +7.0V to +7.0V to +5.0mA
to +5.5V to VCC
twice the rated IOL mA

Note Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

TA VCC /

Parameter Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate

Data Input Enable Input

Rating to +85°C +4.5V to +5.5V
50mV/ns 20mV/ns
1993 Fairchild Semiconductor Corporation
74ABT373 Octal Transparent Latch with 3-STATE Outputs

DC Electrical Characteristics

Parameter

VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage

VOL Output LOW Voltage IIH Input HIGH Current

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Datasheet ID: 74ABT373CMSA 513055