CY7C09569V-100BBC

CY7C09569V-100BBC Datasheet

CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3 V 16 K / 32 K x 36 Synchronous Dual-Port Static RAM

Part	Datasheet
CY7C09569V-100BBC	CY7C09569V-100BBC (pdf)

Related Parts	Information
CY7C09579V-83AXC	CY7C09579V-83AXC
CY7C09579V-83AC	CY7C09579V-83AC

PDF Datasheet Preview
CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3 V 16 K / 32 K x 36 Synchronous Dual-Port Static RAM CY7C09569V CY7C09579V V 16 K / 32 K x 36 Synchronous Dual-Port Static RAM V 16 K / 32 K x 36 Synchronous Dual-Port Static RAM • True dual-ported memory cells which allow simultaneous access of the same memory location • Two flow-through/pipelined devices 16 K x 36 organization CY7C09569V 32 K x 36 organization CY7C09579V • 0.25-micron CMOS for optimum speed/power • Three modes Flow-through Pipelined Burst • Bus-matching capabilities on right port x 36 to x 18 or x 9 • Byte-select capabilities on left port • 100-MHz pipelined operation • High-speed clock to data access 5/6 ns • V low operating power Active = 250 mA typical Standby = 10 typical • Fully synchronous interface for ease of use • Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in flow-through and pipelined modes • Counter address read back via I/O lines • Single chip enable • Automatic power-down • Commercial and industrial temperature ranges • Compact package 144-pin TQFP 20 x 20 x mm 144-pin Pb-free TQFP 20 x 20 x mm 172-ball BGA 1.0-mm pitch 15 x 15 x mm Selection Guide fMAX2 pipelined Maximum access time clock to data, pipelined Typical operating current ICC Typical standby current for ISB1 both ports TTL level Typical standby current for ISB3 both ports CMOS level Functional Description The CY7C09569V and CY7C09579V are high-speed V synchronous CMOS 16 K and 32 K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 5 ns pipelined . Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the external R/W LOW duration. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE for one clock cycle will power down the internal circuitry to reduce the static power consumption. In the pipelined mode, one cycle is required with CE LOW to reactivate the outputs. Counter Enable Inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe ADS . When the port’s Count Enable CNTEN is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset CNTRST is used to reset the burst counter. Parts are available in 144-pin Thin Quad Plastic Flatpack TQFP , 144-pin Pb-free Thin Quad Plastic Flatpack TQFP and 172-ball Grid Array BGA packages. CY7C09569V / CY7C09579V -100 Unit MHz ns mA • San Jose, CA 95134-1709 • 408-943-2600 CY7C09569V CY7C09579V Logic Block Diagram R/WL OEL CEL FT/PipeL Left Port Control Logic CLKL ADSL CNTENL CNTRSTL 14/15 Counter/ Address Register Decode I/O Control I/O Control True Dual-Ported RAM Array Right Port Control Logic Match Ordering Information 28 16 K x 36 V Synchronous Dual-Port SRAM 28 32K x 36 V Synchronous Dual-Port SRAM 28 Ordering Code Definitions 28 Package Diagrams 29 Acronyms 31 Document Conventions 31 Units of Measure 31 Document History Page 32 Sales, Solutions, and Legal Information 33 Worldwide Sales and Design Support 33 Products 33 PSoC Solutions 33 Page 3 of 33 CY7C09569V CY7C09579V Pin Configurations Figure 144-pin TQFP 20 x 20 x mm pinout Top View I/O32R I/O31R I/O30R I/O29R I/O28R I/O27R I/O17R I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R I/O9R I/O9L I/O10L I/O11L I/O12L I/O13L I/O14L I/O15L I/O16L I/O17L I/O27L I/O28L I/O29L I/O30L I/O31L I/O32L I/O33L I/O34L I/O35L Ordering Information 16 K x 36 V Synchronous Dual-Port SRAM Speed MHz Ordering Code 100 CY7C09569V-100AXC CY7C09569V-100BBC Package Name A144 BB172 Package Type 144-pin TQFP Pb-free 172-ball BGA 32K x 36 V Synchronous Dual-Port SRAM Speed MHz Ordering Code 100 CY7C09579V-100AC CY7C09579V-100AXC CY7C09579V-100BBC 83 CY7C09579V-83AC CY7C09579V-83AXC CY7C09579V-83BBC Package Name A144 BB172 A144 BB172 Package Type 144-pin TQFP 144-pin TQFP Pb-free 172-ball BGA 144-pin TQFP 144-pin TQFP Pb-free 172-ball BGA Ordering Code Definitions C 09 5 X9 V - XXX X Temperature Range C = Commercial X = Pb-free RoHS Compliant Package Type X = A or BB A = 144-pin TQFP BB = 172-ball BGA Speed Grade XXX = 83 MHz or 100 MHz V = V Depth X9, where X = 6 or 7 6 = 16K 7 = 32K 5 = Width x 36 09 = Sync Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Device CY7C09569V CY7C09579V Operating Range Commercial Operating Range Commercial Page 28 of 33 CY7C09569V CY7C09579V Package Diagrams Figure 144-pin TQFP 20 x 20 x mm A144SA Package Outline, 51-85047 51-85047 D Page 29 of 33 CY7C09569V CY7C09579V Package Diagrams continued Figure 172-ball FBGA 15 x 15 x mm BB172 Package Outline, 51-85114 51-85114 D Page 30 of 33 Acronyms Acronym address strobe ball grid array chip enable CMOS complementary metal oxide semiconductor CNTEN count enable CNTRST counter reset input/output least significant bit most significant bit output enable SRAM static random access memory TQFP thin quad flat pack transistor-transistor logic CY7C09569V CY7C09579V Document Conventions Units of Measure See ECN Updated Ordering Information Added Pb-free Information . 2897215 RAME 03/22/10 Updated Ordering Information Removed inactive parts . Updated Package Diagrams. 3110406 ADMU 12/14/10 Added Ordering Code Definitions. Minor edits and updated in new template. 3162642 ADMU 02/04/11 Updated Selection Guide Removed speed bin -67 related information . Updated Operating Range Removed Industrial Temperature Range information . Updated Electrical Characteristics Removed speed bin -67 related information . Updated Switching Characteristics Removed speed bin -67 related information . Added Acronyms and Units of Measure. 3352391 ADMU 3702863 SMCH 08/20/2012 Updated Logic Block Diagram Aligned all the objects correctly . Updated Switching Waveforms Updated Figure 18 Aligned the naming of objects correctly , updated Figure 19 Aligned the naming of objects correctly , updated Figure 20 Aligned the naming of objects correctly . Updated Right Port Operation Updated the columns Data on 1st Cycle, Data on 2nd Cycle, Data on 3rd Cycle and Data on 4th Cycle . Updated Bus Match Operation Updated Byte 9-bit Operation description . Replaced Logic ‘0’ with Logic LOW and replaced Logic ‘1’ with Logic HIGH across the document. Page 32 of 33 CY7C09569V CY7C09579V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 33 of 33 FLEx36 is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

PDF Datasheet Preview

CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3 V 16 K / 32 K x 36 Synchronous Dual-Port Static RAM

CY7C09569V CY7C09579V

V 16 K / 32 K x 36 Synchronous Dual-Port Static RAM

V 16 K / 32 K x 36 Synchronous Dual-Port Static RAM
• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two flow-through/pipelined devices 16 K x 36 organization CY7C09569V 32 K x 36 organization CY7C09579V
• 0.25-micron CMOS for optimum speed/power
• Three modes Flow-through Pipelined Burst
• Bus-matching capabilities on right port x 36 to x 18 or x 9
• Byte-select capabilities on left port
• 100-MHz pipelined operation
• High-speed clock to data access 5/6 ns
• V low operating power Active = 250 mA typical Standby = 10 typical
• Fully synchronous interface for ease of use
• Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in flow-through and pipelined modes
• Counter address read back via I/O lines
• Single chip enable
• Automatic power-down
• Commercial and industrial temperature ranges
• Compact package 144-pin TQFP 20 x 20 x mm 144-pin Pb-free TQFP 20 x 20 x mm 172-ball BGA 1.0-mm pitch 15 x 15 x mm

Selection Guide
fMAX2 pipelined Maximum access time clock to data, pipelined Typical operating current ICC Typical standby current for ISB1 both ports TTL level Typical standby current for ISB3 both ports CMOS level

Functional Description

The CY7C09569V and CY7C09579V are high-speed V synchronous CMOS 16 K and 32 K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 5 ns pipelined . Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the external R/W LOW duration. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE for one clock cycle will power down the internal circuitry to reduce the static power consumption. In the pipelined mode, one cycle is required with CE LOW to reactivate the outputs. Counter Enable Inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe ADS . When the port’s Count Enable CNTEN is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset CNTRST is used to reset the burst counter. Parts are available in 144-pin Thin Quad Plastic Flatpack TQFP , 144-pin Pb-free Thin Quad Plastic Flatpack TQFP and 172-ball Grid Array BGA packages.

CY7C09569V / CY7C09579V
-100

Unit

MHz ns mA
• San Jose, CA 95134-1709
• 408-943-2600

CY7C09569V CY7C09579V

Logic Block Diagram

R/WL OEL CEL FT/PipeL

Left Port Control Logic

CLKL ADSL CNTENL CNTRSTL
14/15

Counter/ Address Register Decode

I/O Control

I/O Control

True Dual-Ported RAM Array

Right Port Control Logic

Match
Ordering Information 28 16 K x 36 V Synchronous Dual-Port SRAM 28 32K x 36 V Synchronous Dual-Port SRAM 28 Ordering Code Definitions 28

Package Diagrams 29 Acronyms 31 Document Conventions 31

Units of Measure 31 Document History Page 32 Sales, Solutions, and Legal Information 33

Worldwide Sales and Design Support 33 Products 33 PSoC Solutions 33

Page 3 of 33

CY7C09569V CY7C09579V

Pin Configurations

Figure 144-pin TQFP 20 x 20 x mm pinout Top View

I/O32R

I/O31R

I/O30R

I/O29R

I/O28R

I/O27R

I/O17R

I/O16R

I/O15R

I/O14R

I/O13R

I/O12R

I/O11R

I/O10R

I/O9R

I/O9L

I/O10L

I/O11L

I/O12L

I/O13L

I/O14L

I/O15L

I/O16L

I/O17L

I/O27L

I/O28L

I/O29L

I/O30L

I/O31L

I/O32L

I/O33L

I/O34L

I/O35L
Ordering Information
16 K x 36 V Synchronous Dual-Port SRAM

Speed MHz
Ordering Code
100 CY7C09569V-100AXC

CY7C09569V-100BBC

Package Name A144 BB172

Package Type
144-pin TQFP Pb-free 172-ball BGA
32K x 36 V Synchronous Dual-Port SRAM

Speed MHz
Ordering Code
100 CY7C09579V-100AC

CY7C09579V-100AXC

CY7C09579V-100BBC
83 CY7C09579V-83AC

CY7C09579V-83AXC

CY7C09579V-83BBC

Package Name A144 BB172 A144 BB172

Package Type
144-pin TQFP 144-pin TQFP Pb-free 172-ball BGA 144-pin TQFP 144-pin TQFP Pb-free 172-ball BGA
Ordering Code Definitions

C 09 5

X9 V - XXX X

Temperature Range C = Commercial X = Pb-free RoHS Compliant Package Type X = A or BB A = 144-pin TQFP BB = 172-ball BGA Speed Grade XXX = 83 MHz or 100 MHz V = V Depth X9, where X = 6 or 7 6 = 16K 7 = 32K 5 = Width x 36 09 = Sync Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Device

CY7C09569V CY7C09579V

Operating Range

Commercial

Operating Range

Commercial

Page 28 of 33

CY7C09569V CY7C09579V

Package Diagrams

Figure 144-pin TQFP 20 x 20 x mm A144SA Package Outline, 51-85047
51-85047 *D

Page 29 of 33

CY7C09569V CY7C09579V

Package Diagrams continued

Figure 172-ball FBGA 15 x 15 x mm BB172 Package Outline, 51-85114
51-85114 *D

Page 30 of 33

Acronyms

Acronym
address strobe
ball grid array
chip enable

CMOS
complementary metal oxide semiconductor

CNTEN count enable

CNTRST counter reset
input/output
least significant bit
most significant bit
output enable

SRAM
static random access memory

TQFP
thin quad flat pack
transistor-transistor logic

CY7C09569V CY7C09579V

Document Conventions

Units of Measure
See ECN Updated Ordering Information Added Pb-free Information .
2897215 RAME
03/22/10 Updated Ordering Information Removed inactive parts .

Updated Package Diagrams.
3110406 ADMU
12/14/10 Added Ordering Code Definitions.

Minor edits and updated in new template.
3162642 ADMU
02/04/11 Updated Selection Guide Removed speed bin -67 related information .

Updated Operating Range Removed Industrial Temperature Range
information .

Updated Electrical Characteristics Removed speed bin -67 related
information .

Updated Switching Characteristics Removed speed bin -67 related
information .

Added Acronyms and Units of Measure.
3352391 ADMU
3702863 SMCH 08/20/2012 Updated Logic Block Diagram Aligned all the objects correctly .

Updated Switching Waveforms Updated Figure 18 Aligned the naming of
objects correctly , updated Figure 19 Aligned the naming of objects correctly ,
updated Figure 20 Aligned the naming of objects correctly .

Updated Right Port Operation Updated the columns Data on 1st Cycle, Data
on 2nd Cycle, Data on 3rd Cycle and Data on 4th Cycle .

Updated Bus Match Operation Updated Byte 9-bit Operation description .

Replaced Logic ‘0’ with Logic LOW and replaced Logic ‘1’ with Logic HIGH
across the document.

Page 32 of 33

CY7C09569V CY7C09579V

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 33 of 33

FLEx36 is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C09569V-100BBC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C09569V-100BBC 507876