CY7C09569V-100AC

CY7C09569V-100AC Datasheet

CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM

Part	Datasheet
CY7C09569V-100AC	CY7C09569V-100AC (pdf)

Related Parts	Information
CY7C09569V-83AXCT	CY7C09569V-83AXCT
CY7C09569V-83AXC	CY7C09569V-83AXC
CY7C09579V-83AXI	CY7C09579V-83AXI

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CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM CY7C09569V CY7C09579V 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices 16K x 36 organization CY7C09569V 32K x 36 organization CY7C09579V • 0.25-micron CMOS for optimum speed/power • Three modes Flow-Through Pipelined Burst • Bus-Matching Capabilities on Right Port x36 to x18 or x9 • Byte-Select Capabilities on Left Port • 100-MHz Pipelined Operation • High-speed clock to data access 5/6/8 ns • 3.3V Low operating power Active = 250 mA typical Standby = 10 uA typical • Fully synchronous interface for ease of use • Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in Flow-Through and Pipelined modes • Counter Address Read Back via I/O lines • Single Chip Enable • Automatic power-down • Commercial and Industrial Temperature Ranges • Compact package 144-Pin TQFP 20 x 20 x mm 144-Pin Pb-Free TQFP 20 x 20 x mm 172-Ball BGA 1.0-mm pitch 15 x 15 x mm Logic Block Diagram R/WL OEL CEL FT/PipeL Left Port Control Logic CLKL ADSL CNTENL CNTRSTL 14/15 Counter/ Address Register Decode Note for 16K for 32K devices. I/O Control I/O Control True Dual-Ported RAM Array Right Port Control Logic Match Counter/ Address Register Decode R/WR OER CER FT/PipeR 9/18/36 I/OR 14/15 BM SIZE CLKR ADSR CNTENR CNTRSTR Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C09569V CY7C09579V Functional Description The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 5 ns pipelined . Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the external R/W LOW duration. The internal write pulse is selftimed to allow the shortest possible cycle times. A HIGH on CE for one clock cycle will power down the internal circuitry to reduce the static power consumption. In the pipelined mode, one cycle is required with CE LOW to reactivate the outputs. Counter Enable Inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe ADS . When the port’s Count Enable CNTEN is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset CNTRST is used to reset the burst counter. All parts are available in 144-Pin Thin Quad Plastic Flatpack TQFP , 144-Pin Pb-Free Thin Quad Plastic Flatpack TQFP and 172-Ball Grid Array BGA packages. Page 2 of 30 Pin Configurations 144-Pin Thin Quad Flatpack TQFP Top View Ordering Information 16K x36 3.3V Synchronous Dual-Port SRAM Speed MHz Ordering Code Package Name CY7C09569V-100AC CY7C09569V-100AXC CY7C09569V-100BBC CY7C09569V-83AC CY7C09569V-83AXC CY7C09569V-83BBC CY7C09569V-67AC CY7C09569V-67BBC A144 BB172 A144 BB172 A144 BB172 Package Type 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA CY7C09569V CY7C09579V Operating Range Commercial 32K x36 3.3V Synchronous Dual-Port SRAM Speed MHz Ordering Code CY7C09579V-100AC CY7C09579V-100AXC CY7C09579V-100BBC Package Name A144 A144 BB172 CY7C09579V-83AC CY7C09579V-83AXC CY7C09579V-83AI CY7C09579V-83AXI CY7C09579V-83BBC CY7C09579V-83BBI CY7C09579V-67AC CY7C09579V-67BBC A144 BB172 A144 BB172 Package Type 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA Operating Range Commercial Industrial Commercial Industrial Commercial Page 27 of 30 Package Diagrams CY7C09569V CY7C09579V 144-Pin Plastic Thin Quad Flat Pack TQFP A144 144-Pin Pb-Free Plastic Thin Quad Flat Pack TQFP A144 51-85047-A Page 28 of 30 Package Diagrams continued 172-Ball FBGA 15 x 15 x mm BB172 CY7C09569V CY7C09579V 51-85114-B FLeX36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 29 of 30 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C09569V CY7C09579V Document History Page Document Title CY7C09569V/CY7C09579V 16K/ 32K x 36 FLEx36 Synchronous Dual-Port Static RAM Document Number 38-06054 Issue Date Orig. of Change Description of Change 110213 12/16/01 SZV Change from Spec number 38-00743 to 38-06054 122304 12/27/02 RBI Power up requirements added to Maximum Ratings Information 349775 See ECN RUY Added Pb-Free Information Page 30 of 30

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CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM

CY7C09569V CY7C09579V
3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM
• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two Flow-Through/Pipelined devices 16K x 36 organization CY7C09569V 32K x 36 organization CY7C09579V
• 0.25-micron CMOS for optimum speed/power
• Three modes

Flow-Through Pipelined Burst
• Bus-Matching Capabilities on Right Port x36 to x18 or x9
• Byte-Select Capabilities on Left Port
• 100-MHz Pipelined Operation
• High-speed clock to data access 5/6/8 ns
• 3.3V Low operating power Active = 250 mA typical Standby = 10 uA typical
• Fully synchronous interface for ease of use
• Burst counters increment addresses internally

Shorten cycle times Minimize bus noise Supported in Flow-Through and Pipelined modes
• Counter Address Read Back via I/O lines
• Single Chip Enable
• Automatic power-down
• Commercial and Industrial Temperature Ranges
• Compact package 144-Pin TQFP 20 x 20 x mm 144-Pin Pb-Free TQFP 20 x 20 x mm 172-Ball BGA 1.0-mm pitch 15 x 15 x mm

Logic Block Diagram

R/WL OEL CEL FT/PipeL

Left Port Control Logic

CLKL ADSL CNTENL CNTRSTL
14/15

Counter/ Address Register Decode

Note for 16K for 32K devices.

I/O Control

I/O Control

True Dual-Ported RAM Array

Right Port Control Logic

Match

Counter/ Address Register Decode

R/WR OER CER FT/PipeR
9/18/36

I/OR
14/15

BM SIZE

CLKR ADSR

CNTENR CNTRSTR

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C09569V CY7C09579V

Functional Description

The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 5 ns pipelined . Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin.

Each port contains a burst counter on the input address register. The internal write pulse width is independent of the external R/W LOW duration. The internal write pulse is selftimed to allow the shortest possible cycle times.

A HIGH on CE for one clock cycle will power down the internal circuitry to reduce the static power consumption. In the pipelined mode, one cycle is required with CE LOW to reactivate the outputs.

Counter Enable Inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe ADS . When the port’s Count Enable CNTEN is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset CNTRST is used to reset the burst counter.

All parts are available in 144-Pin Thin Quad Plastic Flatpack TQFP , 144-Pin Pb-Free Thin Quad Plastic Flatpack TQFP and 172-Ball Grid Array BGA packages.

Page 2 of 30

Pin Configurations
144-Pin Thin Quad Flatpack TQFP Top View
Ordering Information
16K x36 3.3V Synchronous Dual-Port SRAM

Speed MHz
Ordering Code

Package Name

CY7C09569V-100AC

CY7C09569V-100AXC

CY7C09569V-100BBC

CY7C09569V-83AC

CY7C09569V-83AXC

CY7C09569V-83BBC

CY7C09569V-67AC

CY7C09569V-67BBC

A144 BB172 A144 BB172 A144 BB172

Package Type 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA

CY7C09569V CY7C09579V

Operating Range

Commercial
32K x36 3.3V Synchronous Dual-Port SRAM

Speed MHz
Ordering Code CY7C09579V-100AC CY7C09579V-100AXC CY7C09579V-100BBC

Package Name

A144

A144

BB172

CY7C09579V-83AC

CY7C09579V-83AXC

CY7C09579V-83AI

CY7C09579V-83AXI

CY7C09579V-83BBC

CY7C09579V-83BBI

CY7C09579V-67AC

CY7C09579V-67BBC

A144 BB172 A144 BB172

Package Type 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 144-Pin Thin Quad Flat Pack 144-Pin Pb-Free Thin Quad Flat Pack 172-Ball Grid Array BGA 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA

Operating Range

Commercial Industrial Commercial Industrial Commercial

Page 27 of 30

Package Diagrams

CY7C09569V CY7C09579V
144-Pin Plastic Thin Quad Flat Pack TQFP A144 144-Pin Pb-Free Plastic Thin Quad Flat Pack TQFP A144
51-85047-*A

Page 28 of 30

Package Diagrams continued
172-Ball FBGA 15 x 15 x mm BB172

CY7C09569V CY7C09579V
51-85114-*B

FLeX36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 29 of 30

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C09569V CY7C09579V

Document History Page

Document Title CY7C09569V/CY7C09579V 16K/ 32K x 36 FLEx36 Synchronous Dual-Port Static RAM Document Number 38-06054

Issue Date

Orig. of Change Description of Change
110213 12/16/01

SZV Change from Spec number 38-00743 to 38-06054
122304 12/27/02

RBI Power up requirements added to Maximum Ratings Information
349775 See ECN RUY Added Pb-Free Information

Page 30 of 30

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C09569V-100AC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C09569V-100AC 507875