CY7C09449PVA-AC

CY7C09449PVA-AC Datasheet

CY7C09449PVA-AC

Part	Datasheet
CY7C09449PVA-AC	CY7C09449PVA-AC (pdf)

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CY7C09449PVA-AC 128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP Functional Overview • 128 Kb of dual-ported shared memory • Master and target PCI Specification compliant interface • Embedded host bridge capability • Direct interface to many microprocessors • I2O message transport unit includes four 32-bit, 32 entry FIFO • Local bus clock rates up to 50 MHz • Single 3.3V power supply including compatibility with 3V and 5V PCI bus signaling • 160-pin thin plastic quad flat package Introduction The CY7C09449PVA is one of the PCI interface controllers in the Cypress Semiconductor PCI-DP family. The CY7C09449PVA provides a PCI master and target interface with direct connections to many popular microprocessors. It provides 128 Kb of dual-port SRAM that is used as shared memory between the local microprocessor and the PCI bus. An I2O message unit, complete with message queues and interrupt capability, is also provided. The CY7C09449PVA allows the designer to interface an application to the PCI bus in a straightforward and inexpensive way. Logic Block Diagram The CY7C09449PVA is composed of several shared resources that allow effective data movement between the local bus and the PCI bus. A primary resource within the CY7C09449PVA is its 128 Kb of dual-port memory. This memory is interfaced to both the PCI bus and a local microprocessor bus. This shared memory is accessed as a target from both buses at the same time for inter process communication. The CY7C09449PVA is directed from both the local and PCI bus to become a PCI bus master and move data into or out of the internal shared memory as a direct memory access DMA . The CY7C09449PVA can DMA across the PCI bus any number of 32-bit double words DWORD , up to 16K bytes. It uses the full bursting capabilities of the PCI bus for maximum efficiency and transfers data over the full 32-bit PCI address space. The CY7C09449PVA implements optional requirements of the PCI specification by selecting the optimum PCI command for each transaction it masters to the PCI bus. This maximizes the overall efficiency of the system platform. PCI bridging functions PCI-to-PCI and Host-to-PCI bridges use the commands to enhance prefetch and cache coherency operations. The CY7C09449PVA requests and gains access to the PCI bus as any master. It does not include a PCI bus arbitration function. Standard PC PCI buses include this function embedded systems may need to implement this function. The CY7C09449PVA provides a direct access mechanism from the local bus to the PCI bus. With it, the local processor directs the CY7C09449PVA to run a PCI bus master cycle of any kind to any address. This means that the CY7C09449PVA runs PCI configuration cycles as a host bridge. Bus Master/Slave Interface Up to 16 KByte Burst Transfers on PCI Bus User-Configurable Target Interface Supports Burst Mode PCI Bus Interface Local Processor Bus Interface PCI Bus 128 Kb Dual-Port Shared Memory I2O Message Transport Unit Operations Registers Local Bus I2C SCL/SDA PCI-DPTM Allows Local Processor Direct Access to PCI Bus Provides Required FIFOs and Interrupt Status Registers AN3042_BD.vsd • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C09449PVA-AC Four First In First Out FIFO storage elements provide another resource to the user. These are accessible from either the PCI bus or the local bus. When the I2O messaging unit functionality of the CY7C09449PVA is used, the four FIFOs become part of the I2O messaging unit. The I2O messaging unit consists of the four FIFOs and the I2O system interrupt registers. The shared memory of the CY7C09449PVA is used to store I2O message frame buffers most of the shared memory is still available for general use. Efficient I2O messaging is realized when the local processor uses the CY7C09449PVA direct access mechanism. It is used to retrieve and post I2O message pointers to other I2O agents. Data transfer of the messages themselves is made very efficient using the CY7C09449PVA PCI DMA controller to burst the message frames to other I2O agents. Interprocess communication is supported by two resources of the CY7C09449PVA the mailbox registers and arbitration flags. When writing to the mailbox registers, a method is available for the local processor to pass data while causing an interrupt to the host, and vice versa. This is enabled by the interrupt mask located in the CY7C09449PVA Operations Registers. The arbitration flags are four pairs of bits that are used to manage resource allocation and sharing between software and system processes. The CY7C09449PVA includes an interrupt controller. There are separate interrupt masks and command and status registers for both PCI bus and local bus. The interrupt sources are DMA completion, mailbox, FIFO not empty also for I2O , FIFO overflow, PCI master abort, PCI target abort, and an external interrupt input pin. This interrupt controller is used to signal interrupts onto the PCI bus and the local bus. The CY7C09449PVA interrupt controller does not perform the interrupt controller function for the PCI bus system. Standard PC PCI systems include this function embedded systems may need to implement this function. An I2C compatible serial interface is provided to allow the use of a serial EEPROM for non-volatile storage of CY7C09449PVA initialization parameters. The parameters are PCI configuration and local bus settings. The CY7C09449PVA optionally accesses the EEPROM after reset and downloads initialization information before responding to PCI or local bus transactions. A wide variety of I2C compatible serial components are available to the local and host processor when connected through this interface. The CY7C09449PVA local bus is a flexible, configurable interface that is designed to readily connect to many industry standard microprocessors. In most cases, no external interface logic “glue” is needed. The following block diagram illustrates a generic application for the CY7C09449PVA. Figure Generic Application Block Diagram PCI Add-In Card or PCI System Host CY7C09449PV 128K Bit Shared Memory Processor Power QUICC, 80x86, DSP, etc. Memory SRAM, DRAM, FLASH, etc. Peripherals Mass Storage, ATM, Special, etc. 14 BURST_STYLE Defines the data ordering protocol of bursts on the local bus. 0 = normal linear bursts default 1 = 486 style burst byte ordering in a burst is 048C 40C8 8C04 C840 13 INT_POL Defines the polarity of the IRQ_OUT output signal. 0 = Active LOW interrupt to the local processor default 1 = Active HIGH interrupt to the local processor 12 BLAST_POL Defines the polarity of the BLAST input signal. 0 = Active LOW default 1 = Active HIGH 11 ALE_POL Defines the polarity of the ALE input signal. 0 = Active LOW1 = Active HIGH default 10 RDYOUT_POL Defines the polarity of the RDY_OUT output signal. 0 = Active LOW default 1 = Active HIGH 9:8 BW Defines the data bus width of the local processor interface. 00 = 8 bit 01 = 16 bit 10 = 32 bit 11 = 32 bit with encoded byte enables per Motorola protocol default Page 41 of 52 [+] Feedback CY7C09449PVA-AC 7 BLASTMODE Determines the function of the BLAST input signal. 0 = BLAST is active only during the last transaction of the burst default 1 = BLAST is active throughout the entire burst, and goes inactive when with RDY_IN or RDY_IN become inactive on the last read or write of the burst. DO NOT set BLASTMODE = 1 when XTND_RDY_OUT = 6 BEMODE Determines the byte enable encoding for 16 and 32 bit Motorola modes. 0 = normal byte enables1 = Motorola byte enable encoding. default 5:4 RWMODE Defines how the READ, WRITE, and address STROBE input signals are interpreted internally and defines the Internal Address Strobe. The active polarity of STROBE is determined by ASMODE. ‘01’ is default. Pin Name RWMODE = 00 RWMODE = 01 RWMODE = 1X READ Not Used READ data used as Internal Strobe WRITE Not Used WRITE data used as Internal Strobe STROBE Internal Address Strobe Internal Address Strobe Not used as Internal Address Strobe 3:2 ASMODE Bit 2 defines the polarity of STROBE input signal. And bit 3 defines the edge of CLKIN used to sample the Internal Address Strobe see field RWMODE for a defining characteristic of the Internal Address Strobe x0 = STROBE is active LOW default x1 = STROBE is active HIGH 0x = Internal Address Strobe rising edge sampled default 1x = Internal Address Strobe falling edge sampled 1 DDIN Delayed Data protocol for validated input data. 0 = input data is valid during the current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. default 1 = input data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active. 0 DDOUT Delayed Data protocol for validated output data. 0 = output data is valid during current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. default 1 = output data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active. Page 42 of 52 [+] Feedback CY7C09449PVA-AC Performance Characteristics Absolute Maximum Ratings [4] Storage Temperature to +125°C Ambient Temperature Under Bias to +85°C Max Operating Current IDD [5, 6] mA Voltage on Any VDD Pin Referenced to +4.0V Voltage on Any Signal Pin Referenced to +7.0V Recommended Operating Environment Ambient Operating Temperature TA0°C to +70°C Supply VDD+3.0V to +3.6V Ground Voltage Reference VSS0.0V FCLK PCI Clock Input Frequency ......CLK0 MHz to 33 MHz FCLKIN Local Bus Clock Ordering Information Ordering Code CY7C09449PVA-AC Package Name 51-85049 Package Type 160-Pin Plastic Thin Quad Flat Pack Operating Range 0°C to +70°C Page 50 of 52 [+] Feedback Package Diagrams CY7C09449PVA-AC Figure 160-Pin Plastic Thin Quad Flat Pack 51-85049 - B Page 51 of 52 [+] Feedback CY7C09449PVA-AC Document History Page Document Title CY7C09449PVA-AC 128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP Document Number 001-40319 Orig. of Change Submission Date Description of Change 2077346 VKN/PYRS See ECN New data sheet A 2722497 RAME 06/23/09 Minor ECN to post the data sheet to the web *B 2732450 RAME 07/07/09 Converted from Preliminary to Final Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All product and company names mentioned in this document are the trademarks of their respective holders. Page 52 of 52 [+] Feedback

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CY7C09449PVA-AC
128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP

Functional Overview
• 128 Kb of dual-ported shared memory
• Master and target PCI Specification compliant interface
• Embedded host bridge capability
• Direct interface to many microprocessors
• I2O message transport unit includes four 32-bit, 32 entry FIFO
• Local bus clock rates up to 50 MHz
• Single 3.3V power supply including compatibility with 3V and
5V PCI bus signaling
• 160-pin thin plastic quad flat package

Introduction

The CY7C09449PVA is one of the PCI interface controllers in the Cypress Semiconductor PCI-DP family. The CY7C09449PVA provides a PCI master and target interface with direct connections to many popular microprocessors. It provides 128 Kb of dual-port SRAM that is used as shared memory between the local microprocessor and the PCI bus. An I2O message unit, complete with message queues and interrupt capability, is also provided. The CY7C09449PVA allows the designer to interface an application to the PCI bus in a straightforward and inexpensive way.

Logic Block Diagram

The CY7C09449PVA is composed of several shared resources that allow effective data movement between the local bus and the PCI bus.

A primary resource within the CY7C09449PVA is its 128 Kb of dual-port memory. This memory is interfaced to both the PCI bus and a local microprocessor bus. This shared memory is accessed as a target from both buses at the same time for inter process communication. The CY7C09449PVA is directed from both the local and PCI bus to become a PCI bus master and move data into or out of the internal shared memory as a direct memory access DMA . The CY7C09449PVA can DMA across the PCI bus any number of 32-bit double words DWORD , up to 16K bytes. It uses the full bursting capabilities of the PCI bus for maximum efficiency and transfers data over the full 32-bit PCI address space.

The CY7C09449PVA implements optional requirements of the PCI specification by selecting the optimum PCI command for each transaction it masters to the PCI bus. This maximizes the overall efficiency of the system platform. PCI bridging functions PCI-to-PCI and Host-to-PCI bridges use the commands to enhance prefetch and cache coherency operations. The CY7C09449PVA requests and gains access to the PCI bus as any master. It does not include a PCI bus arbitration function. Standard PC PCI buses include this function embedded systems may need to implement this function.

The CY7C09449PVA provides a direct access mechanism from the local bus to the PCI bus. With it, the local processor directs the CY7C09449PVA to run a PCI bus master cycle of any kind to any address. This means that the CY7C09449PVA runs PCI configuration cycles as a host bridge.

Bus Master/Slave Interface

Up to 16 KByte Burst Transfers on PCI Bus

User-Configurable Target Interface Supports Burst Mode

PCI Bus Interface Local Processor Bus Interface

PCI Bus
128 Kb Dual-Port Shared Memory

I2O Message Transport Unit

Operations Registers

Local Bus I2C SCL/SDA

PCI-DPTM Allows Local Processor Direct Access to PCI Bus

Provides Required FIFOs and Interrupt Status Registers

AN3042_BD.vsd
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C09449PVA-AC

Four First In First Out FIFO storage elements provide another resource to the user. These are accessible from either the PCI bus or the local bus. When the I2O messaging unit functionality of the CY7C09449PVA is used, the four FIFOs become part of the I2O messaging unit. The I2O messaging unit consists of the four FIFOs and the I2O system interrupt registers. The shared memory of the CY7C09449PVA is used to store I2O message frame buffers most of the shared memory is still available for general use. Efficient I2O messaging is realized when the local processor uses the CY7C09449PVA direct access mechanism. It is used to retrieve and post I2O message pointers to other I2O agents. Data transfer of the messages themselves is made very efficient using the CY7C09449PVA PCI DMA controller to burst the message frames to other I2O agents.

Interprocess communication is supported by two resources of the CY7C09449PVA the mailbox registers and arbitration flags. When writing to the mailbox registers, a method is available for the local processor to pass data while causing an interrupt to the host, and vice versa. This is enabled by the interrupt mask located in the CY7C09449PVA Operations Registers. The arbitration flags are four pairs of bits that are used to manage resource allocation and sharing between software and system processes.

The CY7C09449PVA includes an interrupt controller. There are separate interrupt masks and command and status registers for
both PCI bus and local bus. The interrupt sources are DMA completion, mailbox, FIFO not empty also for I2O , FIFO overflow, PCI master abort, PCI target abort, and an external interrupt input pin. This interrupt controller is used to signal interrupts onto the PCI bus and the local bus. The CY7C09449PVA interrupt controller does not perform the interrupt controller function for the PCI bus system. Standard PC PCI systems include this function embedded systems may need to implement this function.

An I2C compatible serial interface is provided to allow the use of a serial EEPROM for non-volatile storage of CY7C09449PVA initialization parameters. The parameters are PCI configuration and local bus settings. The CY7C09449PVA optionally accesses the EEPROM after reset and downloads initialization information before responding to PCI or local bus transactions. A wide variety of I2C compatible serial components are available to the local and host processor when connected through this interface.

The CY7C09449PVA local bus is a flexible, configurable interface that is designed to readily connect to many industry standard microprocessors. In most cases, no external interface logic “glue” is needed.

The following block diagram illustrates a generic application for the CY7C09449PVA.

Figure Generic Application Block Diagram PCI Add-In Card or PCI System Host

CY7C09449PV
128K Bit Shared Memory

Processor Power QUICC, 80x86, DSP, etc.

Memory SRAM, DRAM, FLASH, etc.

Peripherals

Mass Storage, ATM, Special, etc.
14 BURST_STYLE Defines the data ordering protocol of bursts on the local bus. 0 = normal linear bursts default 1 = 486 style burst byte ordering in a burst is 048C 40C8 8C04 C840
13 INT_POL Defines the polarity of the IRQ_OUT output signal. 0 = Active LOW interrupt to the local processor default 1 = Active HIGH interrupt to the local processor
12 BLAST_POL Defines the polarity of the BLAST input signal. 0 = Active LOW default 1 = Active HIGH
11 ALE_POL Defines the polarity of the ALE input signal. 0 = Active LOW1 = Active HIGH default
10 RDYOUT_POL Defines the polarity of the RDY_OUT output signal. 0 = Active LOW default 1 = Active HIGH
9:8 BW Defines the data bus width of the local processor interface. 00 = 8 bit 01 = 16 bit 10 = 32 bit 11 = 32 bit with encoded byte enables per Motorola protocol default

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CY7C09449PVA-AC
7 BLASTMODE Determines the function of the BLAST input signal. 0 = BLAST is active only during the last transaction of the burst default 1 = BLAST is active throughout the entire burst, and goes inactive when with RDY_IN or RDY_IN become inactive on the last read or write of the burst. DO NOT set BLASTMODE = 1 when XTND_RDY_OUT =
6 BEMODE Determines the byte enable encoding for 16 and 32 bit Motorola modes. 0 = normal byte enables1 = Motorola byte enable encoding. default
5:4 RWMODE Defines how the READ, WRITE, and address STROBE input signals are interpreted internally and defines the Internal Address Strobe. The active polarity of STROBE is determined by ASMODE. ‘01’ is default.

Pin Name

RWMODE = 00

RWMODE = 01

RWMODE = 1X

READ

Not Used

READ data used as Internal Strobe

WRITE

Not Used

WRITE data used as Internal Strobe

STROBE

Internal Address Strobe

Internal Address Strobe

Not used as Internal Address Strobe
3:2 ASMODE Bit 2 defines the polarity of STROBE input signal. And bit 3 defines the edge of CLKIN used to sample the Internal Address Strobe see field RWMODE for a defining characteristic of the Internal Address Strobe x0 = STROBE is active LOW default x1 = STROBE is active HIGH 0x = Internal Address Strobe rising edge sampled default 1x = Internal Address Strobe falling edge sampled
1 DDIN Delayed Data protocol for validated input data. 0 = input data is valid during the current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. default 1 = input data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active.
0 DDOUT Delayed Data protocol for validated output data. 0 = output data is valid during current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. default 1 = output data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active.

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CY7C09449PVA-AC

Performance Characteristics

Absolute Maximum Ratings [4]

Storage Temperature to +125°C

Ambient Temperature Under Bias to +85°C Max Operating Current IDD [5, 6] mA Voltage on Any VDD Pin Referenced to +4.0V Voltage on Any Signal Pin Referenced to +7.0V

Recommended Operating Environment

Ambient Operating Temperature TA0°C to +70°C

Supply VDD+3.0V to +3.6V

Ground Voltage Reference VSS0.0V

FCLK PCI Clock Input Frequency ......CLK0 MHz to 33 MHz

FCLKIN Local Bus

Clock
Ordering Information
Ordering Code CY7C09449PVA-AC

Package Name
51-85049

Package Type 160-Pin Plastic Thin Quad Flat Pack

Operating Range
0°C to +70°C

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Package Diagrams

CY7C09449PVA-AC

Figure 160-Pin Plastic Thin Quad Flat Pack
51-85049 - *B

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CY7C09449PVA-AC

Document History Page

Document Title CY7C09449PVA-AC 128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP Document Number 001-40319

Orig. of Change

Submission Date

Description of Change
2077346 VKN/PYRS See ECN New data sheet
*A 2722497

RAME
06/23/09 Minor ECN to post the data sheet to the web
*B 2732450

RAME
07/07/09 Converted from Preliminary to Final

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All product and company names mentioned in this document are the trademarks of their respective holders.

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C09449PVA-AC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C09449PVA-AC 507874