CY7C09349AV-12AXCT

CY7C09349AV-12AXCT Datasheet

CY7C09359AV3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM

Part	Datasheet
CY7C09349AV-12AXCT	CY7C09349AV-12AXCT (pdf)

Related Parts	Information
CY7C09359AV-9AXC	CY7C09359AV-9AXC

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CY7C09359AV3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM CY7C09349AV CY7C09359AV V 4 K/8 K x 18 Synchronous Dual Port Static RAM V 4 K/8 K x 18 Synchronous Dual Port Static RAM • True dual ported memory cells which allow simultaneous access of the same memory location • Two flow-through/pipelined devices 4 K x 18 organization CY7C09349AV 8 K x 18 organization CY7C09359AV • Three modes Flow-through Pipelined Burst • Pipelined output mode on both ports allows fast 83-MHz operation • 0.35-micron CMOS for optimum speed/power • High-speed clock to data access 9 and 12 ns max Logic Block Diagram R/WL UBL • V low operating power Active = 135 mA typical Standby = 10 µA typical • Fully synchronous interface for easier operation • Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in flow-through and pipelined modes • Dual chip enables for easy depth expansion • Upper and lower byte controls for bus matching • Automatic power-down • Commercial and industrial temperature ranges • Available in 100-pin TQFP R/WR UBR CE0L CE1L CE0R CE1R FT/PipeL CLKL ADSL CNTENL CNTRSTL 1b 0b 1a 0a 0/1 b 12/13 Counter/ Address Register Decode I/O Control I/O Control True Dual Ported RAM Array 0a 1a 0b 1b b 0/1 FT/PipeR Counter/ Address Register Decode 9 12/13 11/12R CLKR ADSR CNTENR CNTRSTR Note for 4 K for 8 K devices. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C09349AV CY7C09359AV Functional Description Switching Waveforms 9 Read/Write and Enable Operation 16 Address Counter Control Operation 16 Ordering Information 17 Package Diagram 18 Acronyms 19 Document Conventions 19 Document History Page 20 Sales, Solutions, and Legal Information 20 Page 3 of 20 [+] Feedback Pin Configuration Figure 100-pin TQFP Top View CY7C09349AV CY7C09359AV A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R A7R A9L A10L A11L [3]A12L NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L 1/012L I/O11L I/O10L 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 CY7C09359AV 8 K x 18 66 65 CY7C09349AV 4 K x 18 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A8R A9R A10R A11R A12R[3] NC LBR UBR CE0R CE1R CNTRSTR R/WR GND OER FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R I/O9L I/O8L VCC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/01R I/O2R I/O3R I/O4R I/O5R I/O6R VCC I/O7R I/O8R I/O9R I/10R Selection Guide fMAX2 MHz pipelined Max access time ns clock to data, pipelined Typical operating current ICC mA Typical standby current for ISB1 mA both ports TTL level Typical standby current for ISB3 µA both ports CMOS level Note This pin is NC for CY7C09349AV. CY7C09349AV CY7C09359AV 67 9 135 20 10 µA CY7C09349AV CY7C09359AV 50 12 115 20 10 µA Page 4 of 20 [+] Feedback CY7C09349AV CY7C09359AV Pin Definitions Left Port ADSL CE0L, CE1L CLKL CNTENL CNTRSTL LBL UBL OEL R/WL FT/PIPEL GND NC VCC Right Port ADSR CE0R, CE1R CLKR CNTENR CNTRSTR LBR UBR OER R/WR FT/PIPER Description Address inputs for 4 K, for 8 K devices . Address strobe input. Used as an address qualifier. This signal should be asserted LOW during normal read or write transactions. Asserting this signal LOW also loads the burst address counter with data present on the I/O pins. Chip enable input. To select either the left or right port, both CE0 and CE1 must be asserted to their active states CE0 VIL and CE1 Clock signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter enable input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter reset input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data bus input/output for x16 devices . Lower byte select input. Asserting this signal LOW enables read and write operations to the lower byte for x18, for x16 of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper byte select input. Same function as LB, but to the upper byte Output enable input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/write enable input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-through/pipelined select input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground input. No connect. Power input. Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage C to +150 C Ambient temperature with power applied C to +125 C Supply voltage to ground potential V to V DC voltage applied to outputs in high Z state V to VCC + V DC input voltage V to VCC + V Output current into outputs LOW 20 mA Static discharge > 2001 V Latch-up current > 200 mA Operating Range Range Commercial Industrial[4] Ordering Information 4 K x 18 V Synchronous Dual-Port SRAM Speed ns 9 12 Ordering Code CY7C09349AV-9AXC CY7C09349AV-12AXC Package Name A100 Package Type 100-pin Pb-free Thin Quad Flat Pack 100-pin Pb-free Thin Quad Flat Pack 8 K x 18 V Synchronous Dual-Port SRAM Speed ns 9 Ordering Code CY7C09359AV-9AXC Package Name A100 Package Type 100-pin Pb-free Thin Quad Flat Pack Ordering Code Definitions CY7C 09 XX9 AV - XX AX C Temperature Range C = Commercial Package Type AX = 100-pin Thin Quad Flat Pack Pb-free Speed Bin XX = 9 or 12 V Density XX9 = 349 or 359 Dual Port SRAM Cypress SRAMs Operating Range Commercial Operating Range Commercial Page 17 of 20 [+] Feedback Package Diagram Figure 100-pin Thin Plastic Quad Flat Pack TQFP A100 CY7C09349AV CY7C09359AV 51-85048 *D Page 18 of 20 [+] Feedback CY7C09349AV CY7C09359AV Acronyms Acronym CE CLK CMOS I/O OE SRAM TQFP Description chip enable clock complementary metal oxide semiconductor Input/output enable static random access memory thin quad flat pack Document Conventions Units of Measure Symbol ns V µA mA mV mW MHz pF °C W Unit of Measure nano seconds Volts micro Amperes milli Amperes milli Volts milli Watts Mega Hertz pico Farad degree Celcius Watts Page 19 of 20 [+] Feedback CY7C09349AV CY7C09359AV Document History Page Document Title CY7C09349AV/CY7C09359AV V 4 K/8 K x 18 Synchronous Dual-Port Static RAM Document Number 001-63888 ECN NO. Issue Date Orig. of Change Description of Change 2998931 09/16/2010 RAME New Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

PDF Datasheet Preview

CY7C09359AV3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM

CY7C09349AV CY7C09359AV

V 4 K/8 K x 18 Synchronous Dual Port Static RAM

V 4 K/8 K x 18 Synchronous Dual Port Static RAM
• True dual ported memory cells which allow simultaneous access of the same memory location
• Two flow-through/pipelined devices 4 K x 18 organization CY7C09349AV 8 K x 18 organization CY7C09359AV
• Three modes Flow-through Pipelined Burst
• Pipelined output mode on both ports allows fast 83-MHz operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 9 and 12 ns max

Logic Block Diagram

R/WL UBL
• V low operating power Active = 135 mA typical Standby = 10 µA typical
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally

Shorten cycle times Minimize bus noise Supported in flow-through and pipelined modes
• Dual chip enables for easy depth expansion
• Upper and lower byte controls for bus matching
• Automatic power-down
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP

R/WR UBR

CE0L

CE1L

CE0R

CE1R

FT/PipeL

CLKL ADSL CNTENL CNTRSTL
1b 0b 1a 0a
0/1 b
12/13

Counter/ Address Register Decode

I/O Control

I/O Control

True Dual Ported RAM Array
0a 1a 0b 1b
b 0/1

FT/PipeR

Counter/ Address Register Decode
9 12/13
11/12R CLKR ADSR

CNTENR CNTRSTR

Note for 4 K for 8 K devices.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C09349AV CY7C09359AV

Functional Description
Switching Waveforms 9 Read/Write and Enable Operation 16 Address Counter Control Operation 16 Ordering Information 17 Package Diagram 18 Acronyms 19 Document Conventions 19 Document History Page 20 Sales, Solutions, and Legal Information 20

Page 3 of 20 [+] Feedback

Pin Configuration

Figure 100-pin TQFP Top View

CY7C09349AV CY7C09359AV

A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R A7R

A9L A10L A11L [3]A12L

NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L 1/012L

I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
10 11

CY7C09359AV 8 K x 18
66 65

CY7C09349AV 4 K x 18
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A8R A9R A10R A11R A12R[3] NC LBR UBR CE0R CE1R CNTRSTR R/WR GND OER FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R

I/O9L I/O8L VCC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/01R I/O2R I/O3R I/O4R I/O5R I/O6R VCC I/O7R I/O8R I/O9R I/10R

Selection Guide
fMAX2 MHz pipelined Max access time ns clock to data, pipelined Typical operating current ICC mA Typical standby current for ISB1 mA both ports TTL level Typical standby current for ISB3 µA both ports CMOS level

Note This pin is NC for CY7C09349AV.

CY7C09349AV CY7C09359AV
67 9 135 20 10 µA

CY7C09349AV CY7C09359AV
50 12 115 20 10 µA

Page 4 of 20 [+] Feedback

CY7C09349AV CY7C09359AV

Pin Definitions

Left Port ADSL

CE0L, CE1L CLKL CNTENL

CNTRSTL LBL

UBL OEL R/WL FT/PIPEL GND NC VCC

Right Port ADSR

CE0R, CE1R CLKR CNTENR

CNTRSTR LBR

UBR OER R/WR FT/PIPER

Description Address inputs for 4 K, for 8 K devices . Address strobe input. Used as an address qualifier. This signal should be asserted LOW during normal read or write transactions. Asserting this signal LOW also loads the burst address counter with data present on the I/O pins. Chip enable input. To select either the left or right port, both CE0 and CE1 must be asserted to their active states CE0 VIL and CE1 Clock signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter enable input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter reset input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data bus input/output for x16 devices . Lower byte select input. Asserting this signal LOW enables read and write operations to the lower byte for x18, for x16 of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper byte select input. Same function as LB, but to the upper byte Output enable input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/write enable input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-through/pipelined select input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground input. No connect. Power input.

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage C to +150 C Ambient temperature with power applied C to +125 C Supply voltage to ground potential V to V DC voltage applied to outputs in high Z state V to VCC + V DC input voltage V to VCC + V

Output current into outputs LOW 20 mA Static discharge > 2001 V Latch-up current > 200 mA

Operating Range

Range Commercial Industrial[4]
Ordering Information
4 K x 18 V Synchronous Dual-Port SRAM

Speed ns 9 12
Ordering Code CY7C09349AV-9AXC CY7C09349AV-12AXC

Package Name A100

Package Type 100-pin Pb-free Thin Quad Flat Pack 100-pin Pb-free Thin Quad Flat Pack
8 K x 18 V Synchronous Dual-Port SRAM

Speed ns 9
Ordering Code CY7C09359AV-9AXC

Package Name A100

Package Type 100-pin Pb-free Thin Quad Flat Pack
Ordering Code Definitions CY7C 09 XX9 AV - XX AX C

Temperature Range C = Commercial Package Type AX = 100-pin Thin Quad Flat Pack Pb-free Speed Bin XX = 9 or 12 V Density XX9 = 349 or 359 Dual Port SRAM Cypress SRAMs

Operating Range

Commercial

Operating Range

Commercial

Page 17 of 20 [+] Feedback

Package Diagram

Figure 100-pin Thin Plastic Quad Flat Pack TQFP A100

CY7C09349AV CY7C09359AV
51-85048 *D

Page 18 of 20 [+] Feedback

CY7C09349AV CY7C09359AV

Acronyms

Acronym CE CLK CMOS I/O OE SRAM TQFP

Description chip enable clock complementary metal oxide semiconductor Input/output enable static random access memory thin quad flat pack

Document Conventions

Units of Measure

Symbol ns V µA mA mV mW MHz pF °C W

Unit of Measure nano seconds Volts micro Amperes milli Amperes milli Volts milli Watts Mega Hertz pico Farad degree Celcius Watts

Page 19 of 20 [+] Feedback

CY7C09349AV CY7C09359AV

Document History Page

Document Title CY7C09349AV/CY7C09359AV V 4 K/8 K x 18 Synchronous Dual-Port Static RAM Document Number 001-63888

ECN NO.

Issue Date

Orig. of Change

Description of Change
2998931 09/16/2010 RAME

New Datasheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C09349AV-12AXCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C09349AV-12AXCT 507871