CY7C09159AV-12AXC

CY7C09159AV-12AXC Datasheet

CY7C09159AV CY7C09169AV3.3V 8K/16K x 9 Synchronous Dual Port Static RAM

Part	Datasheet
CY7C09159AV-12AXC	CY7C09159AV-12AXC (pdf)

Related Parts	Information
CY7C09169AV-12AXC	CY7C09169AV-12AXC
CY7C09169AV-12AXI	CY7C09169AV-12AXI
CY7C09159AV-12AC	CY7C09159AV-12AC

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CY7C09159AV CY7C09169AV3.3V 8K/16K x 9 Synchronous Dual Port Static RAM CY7C09159AV CY7C09169AV 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM • True Dual-Ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices 8K x 9 organization CY7C09159AV 16K x 9 organization CY7C09169AV • Three Modes Flow-Through Pipelined Burst • Pipelined output mode on both ports allows fast 83-MHz operation • 0.35-micron CMOS for optimum speed/power • High-speed clock to data access 9 and 12 ns max. • 3.3V Low operating power Active = 135 mA typical Standby = 10 µA typical • Fully synchronous interface for easier operation • Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in Flow-Through and Pipelined modes • Dual Chip Enables for easy depth expansion • Automatic power-down • Commercial and industrial temperature ranges • Available in 100-pin TQFP • Pb-Free packages available Logic Block Diagram R/WL OEL R/WR OER CE0L CE1L CE0R CE1R FT/PipeL I/O0L−I/O8L A0−A[112]/13L CLKL ADSL CNTENL CNTRSTL 13/14 Counter/ Address Register Decode Notes A0−A12 for 8K A0−A13 for 16K. I/O Control I/O Control True Dual-Ported RAM Array FT/PipeR I/O0R−I/O8R Counter/ Address Register Decode 13/14 A0−[1A]12/13R CLKR ADSR CNTENR CNTRSTR Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C09159AV CY7C09169AV Functional Description The CY7C09159AV and CY7C09169AV are high-speed synchronous CMOS 8K and 16K x 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[2] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns pipelined . Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW- to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe ADS . When the port’s Count Enable CNTEN is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset CNTRST is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack TQFP packages. Note When simultaneously writing to the same location, final value cannot be guaranteed. Ordering Information 8K x9 3.3V Synchronous Dual-Port SRAM Speed ns 9 Ordering Code CY7C09159AV-9AC CY7C09159AV-9AXC CY7C09159AV-12AC CY7C09159AV-12AXC Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 16K x9 3.3V Synchronous Dual-Port SRAM Speed ns Ordering Code CY7C09169AV-9AC CY7C09169AV-12AC CY7C09169AV-12AXC CY7C09169AV-12AI CY7C09169AV-12AXI Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Operating Range Commercial Industrial Package Diagram 100-Pin Thin Plastic Quad Flat Pack TQFP A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack TQFP A100 51-85048-*B All products and company names mentioned in this document may be the trademarks of their respective holders. Page 15 of 16 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C09159AV CY7C09169AV Document History Page Document Title CY7C09159AV/CY7C09169AV 3.3V 8K/16K x 9 Synchronous Dual Port SRAM Document Number 38-06053 Issue Date Orig. of Change Description of Change 110205 11/15/01 SZV Change from Spec number 38-00839 to 38-06053 122303 12/27/02 RBI Power up requirements added to Maximum Ratings Information 393581 See ECN YIM Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C09159AV-9AXC, CY7C09159AV-12AXC, CY7C09169AV-12AXC, CY7C09169AV-12AXI Page 16 of 16 [+] Feedback

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CY7C09159AV CY7C09169AV3.3V 8K/16K x 9 Synchronous Dual Port Static RAM

CY7C09159AV CY7C09169AV
3.3V 8K/16K x 9 Synchronous Dual Port Static RAM
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• Two Flow-Through/Pipelined devices 8K x 9 organization CY7C09159AV 16K x 9 organization CY7C09169AV
• Three Modes Flow-Through Pipelined Burst
• Pipelined output mode on both ports allows fast 83-MHz operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 9 and 12 ns max.
• 3.3V Low operating power Active = 135 mA typical Standby = 10 µA typical
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally

Shorten cycle times Minimize bus noise Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pb-Free packages available

Logic Block Diagram

R/WL OEL

R/WR OER

CE0L

CE1L

CE0R

CE1R

FT/PipeL I/O0L−I/O8L

A0−A[112]/13L CLKL ADSL CNTENL CNTRSTL
13/14

Counter/ Address Register Decode

Notes A0−A12 for 8K A0−A13 for 16K.

I/O Control

I/O Control

True Dual-Ported RAM Array

FT/PipeR I/O0R−I/O8R

Counter/ Address Register Decode
13/14

A0−[1A]12/13R CLKR ADSR

CNTENR CNTRSTR

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C09159AV CY7C09169AV

Functional Description

The CY7C09159AV and CY7C09169AV are high-speed synchronous CMOS 8K and 16K x 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[2] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns pipelined . Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin.

Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW- to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs.

Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe ADS . When the port’s Count Enable CNTEN is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset CNTRST is used to reset the burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack TQFP packages.

Note When simultaneously writing to the same location, final value cannot be guaranteed.
Ordering Information
8K x9 3.3V Synchronous Dual-Port SRAM

Speed ns 9
Ordering Code CY7C09159AV-9AC CY7C09159AV-9AXC CY7C09159AV-12AC CY7C09159AV-12AXC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack
16K x9 3.3V Synchronous Dual-Port SRAM

Speed ns
Ordering Code CY7C09169AV-9AC CY7C09169AV-12AC CY7C09169AV-12AXC CY7C09169AV-12AI CY7C09169AV-12AXI

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack

Operating Range

Commercial

Commercial

Operating Range

Commercial

Industrial

Package Diagram
100-Pin Thin Plastic Quad Flat Pack TQFP A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack TQFP A100
51-85048-*B

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 15 of 16

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY7C09159AV CY7C09169AV

Document History Page

Document Title CY7C09159AV/CY7C09169AV 3.3V 8K/16K x 9 Synchronous Dual Port SRAM Document Number 38-06053

Issue Date

Orig. of Change Description of Change
110205 11/15/01

SZV Change from Spec number 38-00839 to 38-06053
122303 12/27/02

RBI Power up requirements added to Maximum Ratings Information
393581 See ECN

YIM Added Pb-Free Logo
Added Pb-Free parts to ordering information:

CY7C09159AV-9AXC, CY7C09159AV-12AXC, CY7C09169AV-12AXC,

CY7C09169AV-12AXI

Page 16 of 16 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C09159AV-12AXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C09159AV-12AXC 507867