CY7C0851AV-167AXC

CY7C0851AV-167AXC Datasheet

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

Part	Datasheet
CY7C0851AV-167AXC	CY7C0851AV-167AXC (pdf)

Related Parts	Information
CY7C0852AV-133BBC	CY7C0852AV-133BBC
CY7C0851AV-133AXC	CY7C0851AV-133AXC

PDF Datasheet Preview
CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV FLEx36 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation • Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices • Pipelined output mode allows fast operation • 0.18-micron CMOS for optimum speed and power • High-speed clock to data access • 3.3V low power Active as low as 225 mA typ Standby as low as 55 mA typ • Mailbox function for message passing • Global master reset • Separate byte enables on both ports • Commercial and industrial temperature ranges • IEEE 1149.1-compatible JTAG boundary scan • 172-Ball FBGA 1 mm pitch 15 mm x 15 mm • 176-Pin TQFP 24 mm x 24 mm x mm • Counter wrap around control Internal mask register controls counter wrap-around Counter-interrupt flags to indicate wrap-around Memory block retransmit operation • Counter readback on address lines • Mask register readback on address lines • Dual Chip Enables on both ports for easy depth expansion Functional Description The FLEx36 family includes 1M, 2M, 4M, and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally more details to follow . The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt CNTINT flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset MRST . The CY7C0853AV device in this family has limited features. Please see “Address Counter and Mask Register Operations” on page for details. Table Product Selection Guide Density Part Number Max. Speed MHz Max. Access Time - Clock to Data ns Typical operating current mA Package 1-Mbit 32K x 36 CY7C0850AV 176TQFP 172FBGA 2-Mbit 64K x 36 CY7C0851AV 176TQFP 172FBGA 4-Mbit 128K x 36 CY7C0852AV 176TQFP 172FBGA 9-Mbit 256K x 36 CY7C0853AV 133 270 172FBGA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram [1] OEL R/WL B0L B3L CE0L CE1L CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV OER R/WR B0R B1R B2R B3R CE0R CE1R I/O Control I/O Control CNT/MSKL ADSL CNTENL CNTRSTL CLKL CNTINTL INTL Addr. Read Back Ordering Information 256K x 36 9M 3.3V Synchronous CY7C0853AV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 133 CY7C0853AV-133BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0853AV-133BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0853AV-133BBXI 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch Pb-Free 100 CY7C0853AV-100BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0853AV-100BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch 128K x 36 4M 3.3V Synchronous CY7C0852AV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 167 CY7C0852AV-167BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0852AV-167AC 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm CY7C0852AV-167AXC 176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free 133 CY7C0852AV-133BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0852AV-133AC 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm CY7C0852AV-133AXC 176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free CY7C0852AV-133BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0852AV-133AI 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm CY7C0852AV-133AXI 176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free 64K x 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 167 CY7C0851AV-167BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0851AV-167BBXC 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch Pb-Free CY7C0851AV-167AC 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm CY7C0851AV-167AXC 176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free 133 CY7C0851AV-133BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0851AV-133AC 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm CY7C0851AV-133AXC 176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free CY7C0851AV-133BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0851AV-133AI 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm CY7C0851AV-133AXI 176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free 32K x 36 1M 3.3V Synchronous CY7C0850AV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 167 CY7C0850AV-167BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0850AV-167AC 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm 133 CY7C0850AV-133BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0850AV-133AC 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm CY7C0850AV-133BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch CY7C0850AV-133AI 51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm Operating Range Commercial Industrial Commercial Industrial Operating Range Commercial Commercial Industrial Operating Range Commercial Commercial Industrial Operating Range Commercial Industrial Page 28 of 32 [+] Feedback CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Package Diagrams Figure 172-Ball FBGA 15 x 15 x mm 51-85114 51-85114-B Page 29 of 32 [+] Feedback CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Package Diagrams Figure 176-Pin Thin Quad Flat Pack 24 x 24 x mm 51-85132 51-85132-* Page 30 of 32 [+] Feedback CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document History Page Document Title FLEx36 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number 38-06070 ECN NO. Submission Date Added 133-MHz Industrial device to Ordering Information table 210948 See ECN YDT Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF. 231996 See ECN YDT Removed “A particular port can write to a certain location while another port is reading that location.” from Functional Description. 238938 See ECN WWZ Merged 0853 9Mx36 with 0852 4Mx36 and 0851 2Mx36 , add 0850 1M x36 , to the data sheet. Added product selection table. Added JTAG ID code for 1M device. Added note Updated boundary scan section. Updated function description for the merge and addition. 329122 See ECN SPN Updated Marketing part numbers 389877 See ECN KGH Updated Read-to-Write-to-Read timing diagram to reflect accurate bus turnaround scheme. Added ISB5 Changed tRSCNTINT to 10ns Changed tRSF to 10ns Added figure Added figure Added figure Disabled-to-Read-to-Disabled-to-Write Added figure Read-to-Readback-to-Read-to-Read R/W = HIGH Updated Read-to-Write-to-Read timing diagram to correct the data out schemes Updated timing diagram to correct the chip enable, data in, and data out schemes Updated timing diagram to correct the chip enable and output enable schemes Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct the chip enable and output enable schemes 391597 See ECN SPN Updated counter reset section to reflect mirror register behavior 2544945 07/29/08 VKN/AESA Updated Template. Updated ordering information Page 31 of 32 [+] Feedback CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 32 of 32 FLEx36 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

FLEx36 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power

Active as low as 225 mA typ Standby as low as 55 mA typ
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 172-Ball FBGA 1 mm pitch 15 mm x 15 mm
• 176-Pin TQFP 24 mm x 24 mm x mm
• Counter wrap around control Internal mask register controls counter wrap-around Counter-interrupt flags to indicate wrap-around Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth expansion

Functional Description

The FLEx36 family includes 1M, 2M, 4M, and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time.

During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally more details to follow . The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs.

Additional features include readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt CNTINT flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset MRST .

The CY7C0853AV device in this family has limited features. Please see “Address Counter and Mask Register Operations” on page for details.

Table Product Selection Guide

Density

Part Number Max. Speed MHz Max. Access Time - Clock to Data ns Typical operating current mA Package
1-Mbit 32K x 36

CY7C0850AV
176TQFP 172FBGA
2-Mbit 64K x 36

CY7C0851AV
176TQFP 172FBGA
4-Mbit 128K x 36

CY7C0852AV
176TQFP 172FBGA
9-Mbit 256K x 36 CY7C0853AV
133 270 172FBGA
• San Jose, CA 95134-1709
• 408-943-2600
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Logic Block Diagram [1]

OEL R/WL B0L

B3L CE0L CE1L

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

OER R/WR

B0R B1R B2R B3R CE0R CE1R

I/O Control

I/O Control

CNT/MSKL

ADSL

CNTENL

CNTRSTL CLKL CNTINTL

INTL

Addr. Read Back
Ordering Information
256K x 36 9M 3.3V Synchronous CY7C0853AV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
133 CY7C0853AV-133BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0853AV-133BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0853AV-133BBXI
172-Ball Grid Array 15 x 15 x mm with 1 mm pitch Pb-Free
100 CY7C0853AV-100BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0853AV-100BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch
128K x 36 4M 3.3V Synchronous CY7C0852AV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
167 CY7C0852AV-167BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0852AV-167AC
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm

CY7C0852AV-167AXC
176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free
133 CY7C0852AV-133BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0852AV-133AC
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm

CY7C0852AV-133AXC
176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free

CY7C0852AV-133BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0852AV-133AI
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm

CY7C0852AV-133AXI
176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free
64K x 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
167 CY7C0851AV-167BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0851AV-167BBXC
172-Ball Grid Array 15 x 15 x mm with 1 mm pitch Pb-Free

CY7C0851AV-167AC
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm

CY7C0851AV-167AXC
176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free
133 CY7C0851AV-133BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0851AV-133AC
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm

CY7C0851AV-133AXC
176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free

CY7C0851AV-133BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0851AV-133AI
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm

CY7C0851AV-133AXI
176-Pin Thin Quad Flat Pack 24 x 24 x mm Pb-Free
32K x 36 1M 3.3V Synchronous CY7C0850AV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
167 CY7C0850AV-167BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0850AV-167AC
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm
133 CY7C0850AV-133BBC 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0850AV-133AC
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm

CY7C0850AV-133BBI 51-85114 172-Ball Grid Array 15 x 15 x mm with 1 mm pitch

CY7C0850AV-133AI
51-85132 176-Pin Thin Quad Flat Pack 24 x 24 x mm

Operating Range

Commercial Industrial

Commercial Industrial Operating Range

Commercial

Commercial

Industrial

Operating Range

Commercial

Commercial

Industrial

Operating Range

Commercial

Industrial

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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

Package Diagrams

Figure 172-Ball FBGA 15 x 15 x mm 51-85114
51-85114-*B

Page 29 of 32 [+] Feedback

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

Package Diagrams

Figure 176-Pin Thin Quad Flat Pack 24 x 24 x mm 51-85132
51-85132-**

Page 30 of 32 [+] Feedback

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

Document History Page

Document Title FLEx36 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number 38-06070

ECN NO.

Submission Date
Added 133-MHz Industrial device to Ordering Information table
210948 See ECN YDT Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF.
231996 See ECN YDT Removed “A particular port can write to a certain location while another port is
reading that location.” from Functional Description.
238938 See ECN WWZ Merged 0853 9Mx36 with 0852 4Mx36 and 0851 2Mx36 , add 0850 1M x36 ,
to the data sheet.

Added product selection table.

Added JTAG ID code for 1M device.

Added note

Updated boundary scan section.

Updated function description for the merge and addition.
329122 See ECN SPN Updated Marketing part numbers
389877 See ECN KGH Updated Read-to-Write-to-Read timing diagram to reflect accurate bus
turnaround scheme.

Added ISB5 Changed tRSCNTINT to 10ns Changed tRSF to 10ns Added figure

Added figure

Added figure Disabled-to-Read-to-Disabled-to-Write

Added figure Read-to-Readback-to-Read-to-Read R/W = HIGH

Updated Read-to-Write-to-Read timing diagram to correct the data out schemes

Updated timing diagram to correct
the chip enable, data in, and data out schemes

Updated timing diagram to correct
the chip enable and output enable schemes

Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct the
chip enable and output enable schemes
391597 See ECN SPN Updated counter reset section to reflect mirror register behavior
2544945 07/29/08 VKN/AESA Updated Template. Updated ordering information

Page 31 of 32 [+] Feedback

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

PSoC Solutions

General
psoc.cypress.com/solutions

Low Power/Low Voltage
psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
psoc.cypress.com/usb

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 32 of 32

FLEx36 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

More datasheets: TCS3490EVM | K5V2CL43G | JS1300AQ | B39182B7744C810 | 1254 | TOY0064 | VN02 036 0021 1C | 3412N/39H | CY7C0852AV-133BBC | CY7C0851AV-133AXC

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Datasheet ID: CY7C0851AV-167AXC 507864