CY7C0831AV-167AXC

CY7C0831AV-167AXC Datasheet

CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV

Part	Datasheet
CY7C0831AV-167AXC	CY7C0831AV-167AXC (pdf)

Related Parts	Information
CY7C0831AV-133BBXI	CY7C0831AV-133BBXI

PDF Datasheet Preview
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Functional Description • True Dual-Ported Memory Cells that Allow Simultaneous Access of the Same Memory Location • Synchronous Pipelined Operation • Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices • Pipelined Output Mode Allows Fast Operation • micron CMOS for Optimum Speed and Power • High Speed Clock to Data Access • 3.3V Low Power Active as Low as 225 mA typ Standby as Low as 55 mA typ • Mailbox Function for Message Passing • Global Master Reset • Separate Byte Enables on Both Ports • Commercial and Industrial Temperature Ranges • IEEE Compatible JTAG Boundary Scan • 144-Ball FBGA 13 mm x 13 mm pitch • 120 TQFP 14 mm x 14 mm x mm • Pb-Free Packages Available • Counter Wrap Around Control Internal Mask Register Controls Counter Wrap Around Counter-Interrupt Flags to Indicate Wrap Around Memory Block Retransmit Operation The FLEx18 family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit pipelined, synchronous, true dual port static RAMs that are high speed, low power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally more details to follow . The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap around, counter interrupt CNTINT flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset MRST . The CY7C0833AV device in this family has limited features. See Address Counter and Mask Register Operations [16] on page 6 for details. • Counter Readback on Address Lines • Mask Register Readback on Address Lines • Dual Chip Enables on Both Ports for Easy Depth Expansion Table Product Selection Guide Density Part Number Maximum Speed MHz Maximum Access Time Clock to Data ns Typical Operating Current mA Package 512 Kbit 32K x 18 CY7C0837AV 144 FBGA 1 Mbit 64K x 18 CY7C0830AV 120 TQFP 144 FBGA 2 Mbit 128K x 18 CY7C0831AV 120 TQFP 144 FBGA 4 Mbit 256K x 18 CY7C0832AV CY7C0832BV [1] 9 Mbit 512K x 18 CY7C0833AV 120 TQFP 144 FBGA 120 TQFP 144 FBGA Note CY7C0832AV and CY7C0832BV are functionally identical. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram [2] OEL R/WL B0L B1L CE0L CE1L CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV OER R/WR B0R B1R CE0R CE1R I/O Control Ordering Information 512K x 18 9M 3.3V Synchronous CY7C0833AV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 133 CY7C0833AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0833AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch 100 CY7C0833AV-100BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0833AV-100BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch 256K x 18 4M 3.3V Synchronous CY7C0832AV/CY7C0832BV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 167 CY7C0832AV-167BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0832AV-167AC 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm CY7C0832AV-167AXC 120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free 133 CY7C0832AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0832AV-133AC 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm CY7C0832AV-133AXC 120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free CY7C0832AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0832BV-133AI 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm CY7C0832AV-133AXI 120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free 128K x 18 2M 3.3V Synchronous CY7C0831AV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 167 CY7C0831AV-167BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0831AV-167AC 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm CY7C0831AV-167AXC 120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free 133 CY7C0831AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0831AV-133BBXC 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch Pb-Free CY7C0831AV-133AC 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm CY7C0831AV-133AXC 120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free CY7C0831AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0831AV-133BBXI 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch Pb-Free CY7C0831AV-133AI 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm CY7C0831AV-133AXI 120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free 64K x 18 1M 3.3V Synchronous CY7C0830AV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 167 CY7C0830AV-167BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0830AV-167AC 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm 133 CY7C0830AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0830AV-133AC 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm CY7C0830AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0830AV-133AI 51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm Operating Range Commercial Industrial Commercial Industrial Operating Range Commercial Commercial Industrial Operating Range Commercial Commercial Industrial Operating Range Commercial Industrial Page 24 of 28 [+] Feedback CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Ordering Information 32K x 18 512K 3.3V Synchronous CY7C0837AV Dual-Port SRAM Speed MHz Ordering Code Package Diagram Package Type 167 CY7C0837AV-167BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch 133 CY7C0837AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch CY7C0837AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch Package Diagrams Figure 144-Ball FBGA 13 x 13 x mm 51-85141 TOP VIEW A1 CORNER 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M BOTTOM VIEW M C M C A B +-100.40.1540X 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M Operating Range Commercial Commercial Industrial 1.60MAX. C SEATING PLANE C 0.15 4X DIMENSIONS IN MILLIMETERS REFERENCE JEDEC PUBLICATION 95 DESIGN GUIDE 4.14D PKG. WEIGHT gms 51-85141-B Page 25 of 28 [+] Feedback CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Package Diagrams Figure 120-Pin Thin Quad Flatpack 14 x 14 x mm 51-85100 51-85100-* Page 26 of 28 [+] Feedback CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document History Page Document Title FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Document Number 38-06059 ECN No. Orig. of Change Submission Date Description of Change 111473 11/27/01 Change from Spec number 38-01056 to 38-06059 See ECN Corrected Ordering Codes for 0831 devices in the 133 Mhz speed bin. Added CY7C0833AV-133BBI. 461113 SEE ECN Changed VDDIO to VDD typo Added lead Pb -free parts Corrected typo in DC table 2544945 VKN/AESA 07/29/08 Updated Template. Updated ordering information 2668478 VKN/PYRS 02/04/09 Added CY7C0832BV part Added footnote #1 Updated Ordering information table Page 27 of 28 [+] Feedback CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 28 of 28 FLEx18 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV

FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM

Functional Description
• True Dual-Ported Memory Cells that Allow Simultaneous Access of the Same Memory Location
• Synchronous Pipelined Operation
• Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices
• Pipelined Output Mode Allows Fast Operation
• micron CMOS for Optimum Speed and Power
• High Speed Clock to Data Access
• 3.3V Low Power

Active as Low as 225 mA typ Standby as Low as 55 mA typ
• Mailbox Function for Message Passing
• Global Master Reset
• Separate Byte Enables on Both Ports
• Commercial and Industrial Temperature Ranges
• IEEE Compatible JTAG Boundary Scan
• 144-Ball FBGA 13 mm x 13 mm pitch
• 120 TQFP 14 mm x 14 mm x mm
• Pb-Free Packages Available
• Counter Wrap Around Control Internal Mask Register Controls Counter Wrap Around Counter-Interrupt Flags to Indicate Wrap Around Memory Block Retransmit Operation

The FLEx18 family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit pipelined, synchronous, true dual port static RAMs that are high speed, low power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time.

During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally more details to follow . The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs.

Additional features include readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap around, counter interrupt CNTINT flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset MRST .

The CY7C0833AV device in this family has limited features. See Address Counter and Mask Register Operations [16] on page 6 for details.
• Counter Readback on Address Lines
• Mask Register Readback on Address Lines
• Dual Chip Enables on Both Ports for Easy Depth Expansion

Table Product Selection Guide

Density

Part Number Maximum Speed MHz Maximum Access Time Clock to Data ns Typical Operating Current mA Package
512 Kbit 32K x 18 CY7C0837AV
144 FBGA
1 Mbit 64K x 18 CY7C0830AV
120 TQFP 144 FBGA
2 Mbit 128K x 18 CY7C0831AV
120 TQFP 144 FBGA
4 Mbit 256K x 18

CY7C0832AV CY7C0832BV [1]
9 Mbit 512K x 18

CY7C0833AV
120 TQFP 144 FBGA
120 TQFP
144 FBGA

Note CY7C0832AV and CY7C0832BV are functionally identical.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram [2]

OEL R/WL B0L B1L

CE0L CE1L

CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV

OER R/WR

B0R B1R

CE0R CE1R

I/O Control
Ordering Information
512K x 18 9M 3.3V Synchronous CY7C0833AV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
133 CY7C0833AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0833AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch
100 CY7C0833AV-100BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0833AV-100BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch
256K x 18 4M 3.3V Synchronous CY7C0832AV/CY7C0832BV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
167 CY7C0832AV-167BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0832AV-167AC
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm

CY7C0832AV-167AXC
120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free
133 CY7C0832AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0832AV-133AC
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm

CY7C0832AV-133AXC
120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free

CY7C0832AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0832BV-133AI
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm

CY7C0832AV-133AXI
120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free
128K x 18 2M 3.3V Synchronous CY7C0831AV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
167 CY7C0831AV-167BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0831AV-167AC
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm

CY7C0831AV-167AXC
120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free
133 CY7C0831AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0831AV-133BBXC
144-Ball Grid Array 13 x 13 x mm with 1 mm pitch Pb-Free

CY7C0831AV-133AC
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm

CY7C0831AV-133AXC
120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free

CY7C0831AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0831AV-133BBXI
144-Ball Grid Array 13 x 13 x mm with 1 mm pitch Pb-Free

CY7C0831AV-133AI
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm

CY7C0831AV-133AXI
120-Pin Thin Quad Flat Pack 14 x 14 x mm Pb-Free
64K x 18 1M 3.3V Synchronous CY7C0830AV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
167 CY7C0830AV-167BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0830AV-167AC
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm
133 CY7C0830AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0830AV-133AC
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm

CY7C0830AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0830AV-133AI
51-85100 120-Pin Thin Quad Flat Pack 14 x 14 x mm

Operating Range

Commercial Industrial

Commercial Industrial Operating Range

Commercial

Commercial

Industrial

Operating Range

Commercial

Commercial

Industrial

Operating Range

Commercial

Industrial

Page 24 of 28 [+] Feedback

CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Ordering Information
32K x 18 512K 3.3V Synchronous CY7C0837AV Dual-Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
167 CY7C0837AV-167BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch
133 CY7C0837AV-133BBC 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

CY7C0837AV-133BBI 51-85141 144-Ball Grid Array 13 x 13 x mm with 1 mm pitch

Package Diagrams

Figure 144-Ball FBGA 13 x 13 x mm 51-85141

TOP VIEW

A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M

BOTTOM VIEW

M C M C A B
+-100.40.1540X
12 11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M

Operating Range

Commercial

Commercial

Industrial
1.60MAX. C

SEATING PLANE C
0.15 4X

DIMENSIONS IN MILLIMETERS REFERENCE JEDEC PUBLICATION 95

DESIGN GUIDE 4.14D PKG. WEIGHT gms
51-85141-*B

Page 25 of 28 [+] Feedback

CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV

Package Diagrams

Figure 120-Pin Thin Quad Flatpack 14 x 14 x mm 51-85100
51-85100-**

Page 26 of 28 [+] Feedback

CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV

Document History Page

Document Title FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Document Number 38-06059

ECN No.

Orig. of Change

Submission Date

Description of Change
111473
11/27/01 Change from Spec number 38-01056 to 38-06059
See ECN Corrected Ordering Codes for 0831 devices in the 133 Mhz speed bin. Added CY7C0833AV-133BBI.
461113

SEE ECN Changed VDDIO to VDD typo

Added lead Pb -free parts

Corrected typo in DC table
2544945 VKN/AESA 07/29/08 Updated Template. Updated ordering information
2668478 VKN/PYRS 02/04/09 Added CY7C0832BV part

Added footnote #1
Updated Ordering information table

Page 27 of 28 [+] Feedback

CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

PSoC Solutions

General
psoc.cypress.com/solutions

Low Power/Low Voltage
psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
psoc.cypress.com/usb

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 28 of 28

FLEx18 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C0831AV-167AXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C0831AV-167AXC 507863