CY7C057V-12BBC

CY7C057V-12BBC Datasheet

CY7C056V CY7C057V

Part	Datasheet
CY7C057V-12BBC	CY7C057V-12BBC (pdf)

Related Parts	Information
CY7C056V-15AC	CY7C056V-15AC
CY7C057V-15AC	CY7C057V-15AC
CY7C057V-15BBC	CY7C057V-15BBC

PDF Datasheet Preview
25/0251 CY7C056V CY7C057V 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM • True dual-ported memory cells which allow simultaneous access of the same memory location • 16K x 36 organization CY7C056V • 32K x 36 organization CY7C057V • 0.25-micron CMOS for optimum speed/power • High-speed access 12/15/20 ns • Low operating power Active ICC = 250 mA typical Standby ISB3 = 10 µA typical • Fully asynchronous operation • Automatic power-down Logic Block Diagram • Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device • On-Chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Byte Select on Left Port • Bus Matching on Right Port • Depth Expansion via dual chip enables • Pin select for Master or Slave • Commercial and Industrial Temperature Ranges • Compact package 144-Pin TQFP 20 x 20 x mm 172-Ball BGA 1.0-mm pitch 15 x 15 x.51 mm R/WL CE0L CE1L OEL Left Port Control Logic I/O Control I/O Control Right Port Control Logic Match R/WR CE0R CE1R OER BA WA 9/18/36 I/OR BM SIZE 14/15 Address Decode True Dual-Ported RAM Array Address Decode 14/15 14/15 14/15 SEML BUSYL[2] INTL Interrupt Semaphore Arbitration for 16K for 32K devices. BUSY is an output in Master mode and an input in Slave mode. SEMR BUSYR INTR For the most recent information, visit the Cypress web site at Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 CY7C056V CY7C057V Functional Description Ordering Information Speed ns 12 Ordering Code CY7C056V-12AC CY7C056V-12BBC CY7C056V-15AC CY7C056V-15BBC CY7C056V-20AC CY7C056V-20BBC Package Name A144 BB172 A144 BB172 A144 BB172 Package Type 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA Speed ns 12 15 Ordering Code CY7C057V-12AC CY7C057V-12BBC CY7C057V-15AC CY7C057V-15AI CY7C057V-15BBC CY7C057V-15BBI CY7C057V-20AC CY7C057V-20BBC Package Diagrams Package Name A144 BB172 A144 BB172 A144 BB172 Package Type 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Plastic Thin Quad Flat Pack TQFP A144 CY7C056V CY7C057V Operating Range Commercial Operating Range Commercial Industrial Commercial Industrial Commercial 51-85047-A Page 21 of 23 Package Diagrams continued 172-Ball BGA BB172 CY7C056V CY7C057V Page 22 of 23 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C056V CY7C057V Document Title CY7C056V/CY7C057V 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM Document Number 38-06055 Issue Date Orig. of Change Description of Change 110214 12/16/01 SZV Change from Spec number 38-00742 to 38-06055 Page 23 of 23

PDF Datasheet Preview

25/0251

CY7C056V CY7C057V
3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM
• True dual-ported memory cells which allow simultaneous access of the same memory location
• 16K x 36 organization CY7C056V
• 32K x 36 organization CY7C057V
• 0.25-micron CMOS for optimum speed/power
• High-speed access 12/15/20 ns
• Low operating power

Active ICC = 250 mA typical Standby ISB3 = 10 µA typical
• Fully asynchronous operation
• Automatic power-down

Logic Block Diagram
• Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device
• On-Chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Byte Select on Left Port
• Bus Matching on Right Port
• Depth Expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Compact package
144-Pin TQFP 20 x 20 x mm
172-Ball BGA 1.0-mm pitch 15 x 15 x.51 mm

R/WL CE0L CE1L OEL

Left

Port

Control Logic

I/O Control

I/O Control

Right Port Control Logic

Match

R/WR

CE0R CE1R OER BA WA
9/18/36

I/OR

BM SIZE
14/15

Address Decode

True Dual-Ported RAM Array

Address Decode
14/15
14/15
14/15

SEML BUSYL[2] INTL

Interrupt Semaphore Arbitration
for 16K for 32K devices. BUSY is an output in Master mode and an input in Slave mode.

SEMR

BUSYR INTR

For the most recent information, visit the Cypress web site at

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600

CY7C056V CY7C057V

Functional Description
Ordering Information

Speed ns 12
Ordering Code CY7C056V-12AC CY7C056V-12BBC CY7C056V-15AC CY7C056V-15BBC CY7C056V-20AC CY7C056V-20BBC

Package Name A144 BB172 A144 BB172 A144 BB172

Package Type 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA

Speed ns 12 15
Ordering Code CY7C057V-12AC CY7C057V-12BBC CY7C057V-15AC CY7C057V-15AI CY7C057V-15BBC CY7C057V-15BBI CY7C057V-20AC CY7C057V-20BBC

Package Diagrams

Package Name A144 BB172 A144 BB172 A144 BB172

Package Type 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA 172-Ball Grid Array BGA 144-Pin Thin Quad Flat Pack 172-Ball Grid Array BGA
144-Pin Plastic Thin Quad Flat Pack TQFP A144

CY7C056V CY7C057V

Operating Range

Commercial

Operating Range

Commercial Industrial Commercial Industrial Commercial
51-85047-A

Page 21 of 23

Package Diagrams continued
172-Ball BGA BB172

CY7C056V CY7C057V

Page 22 of 23

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C056V CY7C057V

Document Title CY7C056V/CY7C057V 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM Document Number 38-06055

Issue Date

Orig. of Change Description of Change
110214 12/16/01

SZV Change from Spec number 38-00742 to 38-06055

Page 23 of 23

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C057V-12BBC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C057V-12BBC 507861