CY7C028V-25AC

CY7C028V-25AC Datasheet

• 32K x 16 organization CY7C027V • 64K x 16 organization CY7C028V • 32K x 18 organization CY7C037V • 64K x 18 organization CY7C038V • 0.35-micron CMOS for optimum speed/power • High-speed access 15/20/25 ns • Low operating power

Part	Datasheet
CY7C028V-25AC	CY7C028V-25AC (pdf)

Related Parts	Information
CY7C027V-15AC	CY7C027V-15AC
CY7C028V-20AC	CY7C028V-20AC

PDF Datasheet Preview
025/0251 • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 32K x 16 organization CY7C027V • 64K x 16 organization CY7C028V • 32K x 18 organization CY7C037V • 64K x 18 organization CY7C038V • 0.35-micron CMOS for optimum speed/power • High-speed access 15/20/25 ns • Low operating power Active ICC = 115 mA typical Standby ISB3 = 10 µA typical Logic Block Diagram R/WL UBL CY7C027V/028V CY7C037V/038V 3.3V 32K/64K x 16/18 Dual-Port Static RAM • Fully asynchronous operation • Automatic power-down • Expandable data bus to 32/36 bits or more using Mas- ter/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Separate upper-byte and lower-byte control • Dual Chip Enables • Pin select for Master or Slave • Commercial and Industrial temperature ranges • Available in 100-pin TQFP • Pin-compatible and functionally equivalent to IDT70V27 R/WR UBR CE0L CE1L LBL OEL I/O Control I/O Control CE0R CE1R LBR OER 15/16 Address Decode True Dual-Ported RAM Array Address Decode 15/16 15/16 R/WL SEML [4] BUSYL INTL UBL LBL for x16 devices for x18 devices. for x16 devices for x18 devices. Interrupt Semaphore Arbitration 15/16 R/WR SEMR BUSYR INTR UBR LBR for 32K for 64K devices. BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 21, 2000 CY7C027V/028V CY7C037V/038V Functional Description The CY7C027V/028V and CY7037V/038V are low-power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, commu- nications status buffering, and dual-port video/graphics memory. Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select CE pin. Ordering Information 32K x16 3.3V Asynchronous Dual-Port SRAM Speed ns Ordering Code CY7C027V-15AC CY7C027V-20AC CY7C027V-25AC Package Name A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 64K x16 3.3V Asynchronous Dual-Port SRAM Speed ns 15 20 Ordering Code CY7C028V-15AC CY7C028V-20AC CY7C028V-20AI CY7C028V-25AC Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 32K x18 3.3V Asynchronous Dual-Port SRAM Speed ns Ordering Code CY7C037V-15AC CY7C037V-20AC Package Name A100 A100 CY7C037V-25AC A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 64K x18 3.3V Asynchronous Dual-Port SRAM Speed ns 15 20 Ordering Code CY7C038V-15AC CY7C038V-20AC CY7C038V-20AI CY7C038V-25AC Package Name A100 Document #: Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack CY7C027V/028V CY7C037V/038V Operating Range Commercial Operating Range Commercial Industrial Commercial Operating Range Commercial Operating Range Commercial Industrial Commercial Package Diagram CY7C027V/028V CY7C037V/038V Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

PDF Datasheet Preview

025/0251
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 32K x 16 organization CY7C027V
• 64K x 16 organization CY7C028V
• 32K x 18 organization CY7C037V
• 64K x 18 organization CY7C038V
• 0.35-micron CMOS for optimum speed/power
• High-speed access 15/20/25 ns
• Low operating power

Active ICC = 115 mA typical Standby ISB3 = 10 µA typical

Logic Block Diagram

R/WL UBL

CY7C027V/028V CY7C037V/038V
3.3V 32K/64K x 16/18 Dual-Port Static RAM
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70V27

R/WR UBR

CE0L CE1L

LBL OEL

I/O Control

I/O Control

CE0R CE1R

LBR OER
15/16

Address Decode

True Dual-Ported RAM Array

Address Decode
15/16
15/16

R/WL

SEML [4] BUSYL

INTL UBL LBL
for x16 devices for x18 devices. for x16 devices for x18 devices.

Interrupt Semaphore Arbitration
15/16

R/WR

SEMR

BUSYR INTR UBR LBR
for 32K for 64K devices. BUSY is an output in master mode and an input in slave mode.

For the most recent information, visit the Cypress web site at

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600 November 21, 2000

CY7C027V/028V CY7C037V/038V

Functional Description

The CY7C027V/028V and CY7037V/038V are low-power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, commu-
nications status buffering, and dual-port video/graphics memory.

Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select CE pin.
Ordering Information
32K x16 3.3V Asynchronous Dual-Port SRAM

Speed ns
Ordering Code CY7C027V-15AC CY7C027V-20AC CY7C027V-25AC

Package Name

A100

A100

A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
64K x16 3.3V Asynchronous Dual-Port SRAM

Speed ns 15 20
Ordering Code CY7C028V-15AC CY7C028V-20AC CY7C028V-20AI CY7C028V-25AC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
32K x18 3.3V Asynchronous Dual-Port SRAM

Speed ns
Ordering Code CY7C037V-15AC CY7C037V-20AC

Package Name

A100

A100

CY7C037V-25AC

A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
64K x18 3.3V Asynchronous Dual-Port SRAM

Speed ns 15 20
Ordering Code CY7C038V-15AC CY7C038V-20AC CY7C038V-20AI CY7C038V-25AC

Package Name A100

Document #:

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack

CY7C027V/028V CY7C037V/038V

Operating Range

Commercial

Operating Range

Commercial Industrial Commercial

Operating Range

Commercial

Operating Range

Commercial Industrial Commercial

Package Diagram

CY7C027V/028V CY7C037V/038V

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C028V-25AC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C028V-25AC 507857