CY7B951-SXIT

CY7B951-SXIT Datasheet

CY7B951

Part	Datasheet
CY7B951-SXIT	CY7B951-SXIT (pdf)

Related Parts	Information
CY7B951-SXC	CY7B951-SXC
CY7B951-SXCT	CY7B951-SXCT
CY7B951-SXI	CY7B951-SXI

PDF Datasheet Preview
CY7B951 Local Area Network ATM Transceiver • SONET/SDH and ATM Compatible • Compatible with PMC-Sierra PM5345 SUNI • Clock and data recovery from or 155.52-MHz datastream • 155.52-MHz clock multiplication from 19.44-MHz source • 51.84-MHz clock multiplication from 6.48-MHz source • ±1% frequency agility • Line Receiver Inputs No external buffering required • Differential output buffering • • 100K ECL compatible I/O • No output clock “drift” without data transitions • Link Status Indication • Loopback testing Logic Block Diagram • Single +5V supply • 24-pin SOIC • Compatible with fiber optic modules, coaxial cable, and twisted pair media • No external PLL components • Power down options to minimize power or crosstalk • Low operating current <65 mA • µ BiCMOS • Pb-Free Packages Available Functional Description The Local Area Network ATM Transceiver is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system. Pin Configuration Figure SONET/SDH and ATM Interface • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 CY7B951 Pin Descriptions Name RIN± ROUT± RSER± RCLK± CD TSER± TOUT± REFCLK± TCLK± Differential In Receive Input. This line receiver port connects the receive differential serial input data stream to the internal Receive PLL. This PLL will recover the embedded clock RCLK± and data RSER± infor- mation for one of two data rates depending on the state of the MODE pin. These inputs can receive very low amplitude signals and are compatible with all PECL signaling levels. If the RIN± inputs are not being used, connect RIN+ to VCC and to VSS. ECL Out Receive Output. These ECL 100K outputs +5V referenced represent the buffered version of the input data stream RIN± . This output pair can be used for Receiver input data equalization in copper based systems, reducing the system impact of data-dependent jitter. All PECL outputs can be powered down by connecting both outputs to VCC or leaving them both unconnected. ECL Out Recovered Serial Data. These ECL 100K outputs +5V referenced represent the recovered data from the input data stream RIN± . This recovered data is aligned with the recovered clock RCLK± with a sampling window compatible with most data processing devices. ECL Out TTL/ECL In Recovered Clock. These ECL 100K outputs +5V referenced represent the recovered clock from the input data stream RIN± . This recovered clock is used to sample the recovered data RSER± and has timing compatible with most data processing devices. If both the RSER± and the RCLK± are tied to VCC or left unconnected, the entire Receive PLL will be powered down. Carrier Detect. This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output from optical modules or from external transition detection circuitry. When this input is at an ECL HIGH, the input data stream RIN± is recovered normally by the Receive PLL. When this input is at an ECL LOW, the Receive PLL no longer aligns to RIN±, but instead aligns with the frequency. Also, the Link Fault Indicator LFI will transition LOW, and the recovered data outputs RSER will remain LOW regardless of the signal level on the Receive data stream inputs RIN . When the CD input is at a TTL LOW, the internal transitions detection circuitry is disabled. TTL Out Link Fault Indicator. This output indicates the status of the input data stream RIN± . It is controlled by three functions the Carrier Detect CD input, the internal Transition Detector, and the Out of Lock OOL detector. The Transition Detector determines if RIN± contains enough transitions to be accurately recovered by the Receive PLL. The Out of Lock detector determines if RIN± is within the frequency range of the Receive PLL. When CD is HIGH and RIN± has sufficient transitions and is within the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at an ECL LOW or RIN± does not contain sufficient transitions or RIN± is outside the frequency range of the Receive PLL then the LFI output will be LOW. If CD is at a TTL LOW then the LFI output will only transition LOW when the frequency of RIN± is outside the range of the Receive PLL. Differential In Transmit Serial Data. This line receiver port connects the transmit differential serial input data stream to the TOUT transmit buffers. Depending on the state of the LOOP pin, this input port can also be set up to supply the serial input data stream to the Receive PLL. These inputs can receive very low amplitude signals and are compatible with all PECL signalling levels. If the TSER± inputs are not being used, connect TSER+ to VCC and TSER− to VSS. ECL Out Transmit Output. These ECL 100K outputs +5V referenced represent the buffered version of the Transmit data stream TSER± . This Transmit path is used to take weak input signals and rebuffer them to drive low-impedance copper media. Diff/TTL In Reference Clock. This input is the clock frequency reference for the clock and data recovery Receive PLL. REFCLK is multiplied internally by eight and sets the approximate center frequency for the internal Receive PLL to track the incoming bit stream. This input is also multiplied by eight by the frequency multiplier Transmit PLL to produce the bit rate Transmit Clock TCLK± . REFCLK can be connected to either a differential PECL or single-ended TTL frequency source. When either REFCLK+ or REFCLK− is at a TTL LOW, the opposite REFCLK signal becomes a TTL level input. Ordering Information Speed ns 25 Ordering Code CY7B951-SC CY7B951-SXC CY7B951-SI CY7B951-SXI Package Name S24.3 SZ24.3 S24.3 SZ24.3 Package Type 24-Lead 300-Mil Molded SOIC 24-Lead 300-Mil Pb-Free Molded SOIC 24-Lead 300-Mil Molded SOIC 24-Lead 300-Mil Pb-Free Molded SOIC Operating Range Commercial Industrial Page 8 of 10 CY7B951 Package Diagram Figure 24-Lead 300-Mil SOIC S24.3/SZ24.3 NOTE : PIN 1 ID JEDEC STD REF MO-119 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED in mm PER SIDE DIMENSIONS IN INCHES PACKAGE WEIGHT 0.65gms MIN. MAX. PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG. SEATING PLANE TYP. 51-85025-C SUNI is a trademark of PMC-Sierra, Incorporated. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 9 of 10 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7B951 Document History Page Document Title CY7B951 Local Area Network ATM Transceiver Document Number 38-02010 ECN. Issue Date Orig. of Change Description of Change 105848 03/26/01 SZV Changed from Spec number 38-00358 to 38-02010 A 560754 See ECN PCX Added Pb-Free part numbers to ordering information Page 10 of 10

PDF Datasheet Preview

CY7B951

Local Area Network ATM Transceiver
• SONET/SDH and ATM Compatible
• Compatible with PMC-Sierra PM5345 SUNI
• Clock and data recovery from or 155.52-MHz
datastream
• 155.52-MHz clock multiplication from 19.44-MHz source
• 51.84-MHz clock multiplication from 6.48-MHz source
• ±1% frequency agility
• Line Receiver Inputs No external buffering required
• Differential output buffering
•
• 100K ECL compatible I/O
• No output clock “drift” without data transitions
• Link Status Indication
• Loopback testing

Logic Block Diagram
• Single +5V supply
• 24-pin SOIC
• Compatible with fiber optic modules, coaxial cable, and
twisted pair media
• No external PLL components
• Power down options to minimize power or crosstalk
• Low operating current <65 mA
• µ BiCMOS
• Pb-Free Packages Available

Functional Description

The Local Area Network ATM Transceiver is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

Pin Configuration

Figure SONET/SDH and ATM Interface
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

CY7B951

Pin Descriptions

Name RIN± ROUT± RSER± RCLK± CD

TSER± TOUT± REFCLK±

TCLK±

Differential In Receive Input. This line receiver port connects the receive differential serial input data stream to the internal Receive PLL. This PLL will recover the embedded clock RCLK± and data RSER± infor-
mation for one of two data rates depending on the state of the MODE pin. These inputs can receive very low amplitude signals and are compatible with all PECL signaling levels. If the RIN± inputs are
not being used, connect RIN+ to VCC and to VSS.

ECL Out

Receive Output. These ECL 100K outputs +5V referenced represent the buffered version of the input data stream RIN± . This output pair can be used for Receiver input data equalization in copper
based systems, reducing the system impact of data-dependent jitter. All PECL outputs can be
powered down by connecting both outputs to VCC or leaving them both unconnected.

ECL Out

Recovered Serial Data. These ECL 100K outputs +5V referenced represent the recovered data
from the input data stream RIN± . This recovered data is aligned with the recovered clock RCLK± with a sampling window compatible with most data processing devices.

ECL Out TTL/ECL In

Recovered Clock. These ECL 100K outputs +5V referenced represent the recovered clock from the input data stream RIN± . This recovered clock is used to sample the recovered data RSER± and has timing compatible with most data processing devices. If both the RSER± and the RCLK± are tied to VCC or left unconnected, the entire Receive PLL will be powered down.

Carrier Detect. This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output from optical modules or from external transition detection circuitry. When this input is at an ECL HIGH, the input data stream RIN± is recovered normally by the Receive PLL. When this input is at an ECL LOW, the Receive PLL no longer aligns to RIN±, but instead aligns with the frequency. Also, the Link Fault Indicator LFI will transition LOW, and the recovered data outputs RSER will remain LOW regardless of the signal level on the Receive data stream inputs RIN . When the CD input is at a TTL LOW, the internal transitions detection circuitry is disabled.

TTL Out

Link Fault Indicator. This output indicates the status of the input data stream RIN± . It is controlled by three functions the Carrier Detect CD input, the internal Transition Detector, and the Out of Lock OOL detector. The Transition Detector determines if RIN± contains enough transitions to be accurately recovered by the Receive PLL. The Out of Lock detector determines if RIN± is within the frequency range of the Receive PLL. When CD is HIGH and RIN± has sufficient transitions and is within the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at an ECL LOW or RIN± does not contain sufficient transitions or RIN± is outside the frequency range of the Receive PLL then the LFI output will be LOW. If CD is at a TTL LOW then the LFI output will only transition LOW when the frequency of RIN± is outside the range of the Receive PLL.

Differential In Transmit Serial Data. This line receiver port connects the transmit differential serial input data stream
to the TOUT transmit buffers. Depending on the state of the LOOP pin, this input port can also be
set up to supply the serial input data stream to the Receive PLL. These inputs can receive very low amplitude signals and are compatible with all PECL signalling levels. If the TSER± inputs are not being used, connect TSER+ to VCC and TSER− to VSS.

ECL Out

Transmit Output. These ECL 100K outputs +5V referenced represent the buffered version of the

Transmit data stream TSER± . This Transmit path is used to take weak input signals and rebuffer
them to drive low-impedance copper media.

Diff/TTL In

Reference Clock. This input is the clock frequency reference for the clock and data recovery Receive PLL. REFCLK is multiplied internally by eight and sets the approximate center frequency for the internal Receive PLL to track the incoming bit stream. This input is also multiplied by eight by the frequency multiplier Transmit PLL to produce the bit rate Transmit Clock TCLK± . REFCLK can be connected to either a differential PECL or single-ended TTL frequency source. When either REFCLK+ or REFCLK− is at a TTL LOW, the opposite REFCLK signal becomes a TTL level input.
Ordering Information

Speed ns 25
Ordering Code

CY7B951-SC CY7B951-SXC CY7B951-SI CY7B951-SXI

Package Name S24.3 SZ24.3 S24.3 SZ24.3

Package Type
24-Lead 300-Mil Molded SOIC 24-Lead 300-Mil Pb-Free Molded SOIC 24-Lead 300-Mil Molded SOIC 24-Lead 300-Mil Pb-Free Molded SOIC

Operating Range

Commercial Industrial

Page 8 of 10

CY7B951

Package Diagram

Figure 24-Lead 300-Mil SOIC S24.3/SZ24.3

NOTE :

PIN 1 ID

JEDEC STD REF MO-119 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT

DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED in mm PER SIDE

DIMENSIONS IN INCHES

PACKAGE WEIGHT 0.65gms

MIN. MAX.

PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG.

SEATING PLANE

TYP.
51-85025-*C

SUNI is a trademark of PMC-Sierra, Incorporated. All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 9 of 10

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7B951

Document History Page

Document Title CY7B951 Local Area Network ATM Transceiver Document Number 38-02010

ECN.

Issue Date

Orig. of Change

Description of Change
105848 03/26/01

SZV Changed from Spec number 38-00358 to 38-02010
*A 560754 See ECN PCX Added Pb-Free part numbers to ordering information

Page 10 of 10

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7B951-SXIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7B951-SXIT 507835