CY62168DV30LL-55BVXI

CY62168DV30LL-55BVXI Datasheet

CY62168DV30

Part	Datasheet
CY62168DV30LL-55BVXI	CY62168DV30LL-55BVXI (pdf)

Related Parts	Information
CY62168DV30LL-55BVXIT	CY62168DV30LL-55BVXIT

PDF Datasheet Preview
CY62168DV30 16-Mbit 2M x 8 Static RAM • Very high speed 55 ns • Wide voltage range 2.2V 3.6V • Ultra-low active power Typical active current 2 mA f = 1 MHz Typical active current 15 mA f = fMax 55 ns Speed • Ultra-low standby power • Easy memory expansion with CE1, CE2 and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free and non Pb-free 48-ball VFBGA package Functional Description[1] The CY62168DV30 is a high-performance CMOS static RAMs organized as 2048Kbit words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly Logic Block Diagram reduces power consumption. The device can be put into standby mode reducing power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 CE1 HIGH or Chip Enable 2 CE2 LOW. The input/output pins I/O0 through I/O7 are placed in a high-impedance state when deselected Chip Enable 1 CE1 HIGH or Chip Enable 2 CE2 LOW, outputs are disabled OE HIGH , or during a write operation Chip Enable 1 CE1 LOW and Chip Enable 2 CE2 HIGH and WE LOW . Writing to the device is accomplished by taking Chip Enable 1 CE1 LOW and Chip Enable 2 CE2 HIGH and Write Enable WE input LOW. Data on the eight I/O pins I/O0 through I/O7 is then written into the location specified on the address pins A0 through A20 . Reading from the device is accomplished by taking Chip Enable 1 CE1 and Output Enable OE LOW and Chip Enable 2 CE2 HIGH while forcing Write Enable WE HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins I/O0 through I/O7 are placed in a high-impedance state when the device is deselected CE1 LOW and CE2 HIGH , the outputs are disabled OE HIGH , or during a write operation CE1 LOW and CE2 HIGH and WE LOW . See the truth table for a complete description of read and write modes. ROW DECODER SENSE AMPS Data in Drivers 2048K x 8 ARRAY CE1 CE2 COLUMN DECODER POWER DOWN I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 A13 AA1154 A16 AA1178 A19 A20 Note For best-practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Pin Configuration[2] CY62168DV30 48-ball VFBGA Top View DNU OE A0 A1 A2 CE2 DNU A3 A4 CE1 DNU I/O0 DNU A5 A6 DNU I/O4 VSS I/O1 A17 A7 I/O5 VCC VCC I/O2 DNU A16 I/O6 VSS I/O3 DNU A14 A15 DNU I/O7 DNU A20 A12 A13 WE DNU G A18 A8 A9 A10 A11 A19 Product Portfolio Product CY62168DV30LL VCC Range V Min. Typ.[3] Max. Speed ns Power Dissipation Operating ICC mA Ordering Information Speed ns Ordering Code Package Diagram Package Type 55 CY62168DV30LL-55BVI 51-85178 48-ball Fine Pitch BGA 8 x 1 mm CY62168DV30LL-55BVXI 48-ball Fine Pitch BGA 8 x 1 mm Pb-free Please contact your local Cypress sales representative for availability of these parts Package Diagram 48-ball VFBGA 8 x 1 mm 51-85178 Operating Range Industrial TOP VIEW A1 CORNER 12 3 4 5 6 BOTTOM VIEW M C M C A B Ø0.30±0.05 48X A1 CORNER 6 54 3 2 1 C MAX. SEATING PLANE C B 0.15 4X MAX. 51-85178-** MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Page 8 of 9 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62168DV30 Document History Page Document Title CY62168DV30 16-Mbit 2M x 8 Static RAM Document Number 38-05329 ECN NO. Issue Date Orig. of Change Description of Change 118409 09/30/02 GUG New Data Sheet 123693 02/05/03 DPM Changed Advance Information to Preliminary Added package diagram 126556 04/24/03 DPM Minor change sunset owner from DPM to HRT 132869 01/15/04 XRJ Changed Preliminary to Final 272589 See ECN PCI Updated Final data sheet and added Pb-free package. PCI Removed redundant packages from Ordering Information Table Added Address A20 to ball G2 in the Pin Configuration 492895 See ECN VKN Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 70 ns speed bin Removed L power bin from product offering Updated Ordering Information Table Page 9 of 9

PDF Datasheet Preview

CY62168DV30
16-Mbit 2M x 8 Static RAM
• Very high speed 55 ns
• Wide voltage range 2.2V 3.6V
• Ultra-low active power Typical active current 2 mA f = 1 MHz Typical active current 15 mA f = fMax 55 ns Speed
• Ultra-low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball VFBGA
package

Functional Description[1]

The CY62168DV30 is a high-performance CMOS static RAMs organized as 2048Kbit words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly

Logic Block Diagram
reduces power consumption. The device can be put into standby mode reducing power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 CE1 HIGH or Chip Enable 2 CE2 LOW. The input/output pins I/O0 through I/O7 are placed in a high-impedance state when deselected Chip Enable 1 CE1 HIGH or Chip Enable 2 CE2 LOW, outputs are disabled OE HIGH , or during a write operation Chip Enable 1 CE1 LOW and Chip Enable 2 CE2 HIGH and WE LOW .

Writing to the device is accomplished by taking Chip Enable 1 CE1 LOW and Chip Enable 2 CE2 HIGH and Write Enable WE input LOW. Data on the eight I/O pins I/O0 through I/O7 is then written into the location specified on the address pins A0 through A20 .

Reading from the device is accomplished by taking Chip Enable 1 CE1 and Output Enable OE LOW and Chip Enable 2 CE2 HIGH while forcing Write Enable WE HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins I/O0 through I/O7 are placed in a high-impedance state when the device is deselected CE1 LOW and CE2 HIGH , the outputs are disabled OE HIGH , or during a write operation CE1 LOW and CE2 HIGH and WE LOW . See the truth table for a complete description of read and write modes.

ROW DECODER SENSE AMPS

Data in Drivers
2048K x 8 ARRAY

CE1 CE2

COLUMN DECODER

POWER DOWN

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

A13 AA1154 A16 AA1178 A19 A20

Note For best-practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

Pin Configuration[2]

CY62168DV30
48-ball VFBGA Top View

DNU OE A0 A1 A2 CE2

DNU A3 A4 CE1 DNU

I/O0 DNU A5 A6 DNU I/O4

VSS I/O1 A17 A7 I/O5 VCC

VCC I/O2 DNU A16 I/O6 VSS

I/O3 DNU A14 A15 DNU I/O7

DNU A20 A12 A13 WE DNU G

A18 A8 A9 A10 A11 A19

Product Portfolio

Product CY62168DV30LL

VCC Range V Min. Typ.[3] Max.

Speed ns

Power Dissipation

Operating ICC mA
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type
55 CY62168DV30LL-55BVI
51-85178 48-ball Fine Pitch BGA 8 x 1 mm

CY62168DV30LL-55BVXI
48-ball Fine Pitch BGA 8 x 1 mm Pb-free

Please contact your local Cypress sales representative for availability of these parts

Package Diagram
48-ball VFBGA 8 x 1 mm 51-85178

Operating Range

Industrial

TOP VIEW

A1 CORNER 12 3 4 5 6

BOTTOM VIEW

M C M C A B Ø0.30±0.05 48X

A1 CORNER
6 54 3 2 1

C MAX.

SEATING PLANE C

B 0.15 4X

MAX.
51-85178-**

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.

Page 8 of 9

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY62168DV30

Document History Page

Document Title CY62168DV30 16-Mbit 2M x 8 Static RAM Document Number 38-05329

ECN NO.

Issue Date

Orig. of Change

Description of Change
118409 09/30/02 GUG New Data Sheet
123693 02/05/03 DPM Changed Advance Information to Preliminary

Added package diagram
126556 04/24/03 DPM Minor change sunset owner from DPM to HRT
132869 01/15/04

XRJ Changed Preliminary to Final
272589 See ECN

PCI Updated Final data sheet and added Pb-free package.
PCI Removed redundant packages from Ordering Information Table

Added Address A20 to ball G2 in the Pin Configuration
492895 See ECN VKN Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Removed 70 ns speed bin
Removed L power bin from product offering Updated Ordering Information Table

Page 9 of 9

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62168DV30LL-55BVXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY62168DV30LL-55BVXI 507827