CYWB0125AB-BVXI

CYWB0125AB-BVXI Datasheet

CYWB012X Family

Part	Datasheet
CYWB0125AB-BVXI	CYWB0125AB-BVXI (pdf)

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ADVANCE INFORMATION CYWB012X Family West Antioch West Antioch • architecture, allowing simultaneous and independent data paths between processor and USB, and between USB and mass storage • High speed USB at 480 Mbps USB compliant Integrated USB transceiver, smart Serial Interface Engine 16 programmable endpoints • Mass storage device support MMC/MMC+/SD NAND Flash x 8 or x 16, SLC Full NAND management ECC, wear-leveling • Memory-mapped interface to main processor • DMA slave support • Ultra low power, V core operation • Small footprint, 6 x 6 mm VFBGA and WLCSP • Selectable clock input frequencies MHz, 24 MHz, 48 MHz • Expanded mass storage device support MMC/MMC+/SD CE-ATA for micro-HDD NAND Flash x 8 or x 16, SLC Full NAND management ECC, wear-leveling • Expanded selectable clock input frequencies MHz, 24 MHz, 26 MHz, 48 MHz • Cellular Phones • Portable Media Players • Personal Digital Assistants • Digital Cameras • Portable Video Recorder Logic Block Diagram West Bridge Antioch Control Registers 8051 MCU Access Control Processor Interface High-Speed USB XCVR SLIMTM Mass Storage Interface SD/MMC/CE-ATA NAND • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback ADVANCE INFORMATION CYWB012X Family West Antioch is a peripheral mass storage controller that enhances a processor system with flexible mass storage support and high speed USB connectivity. Antioch has three different ports that enable connections among a main processor P-Port , one or more mass storage devices S-Port , and a USB host U-Port . Antioch’s unique SLIM architecture allows these three ports to interact simultaneously and independently of each other. This offers connectivity from USB to Storage typically used for PC high speed data download , from USB to Processor used for synchronization operations , and from Processor to Storage. Connected as a slave to a main processor, Antioch adds support for high speed USB and mass storage access including MMC, MMC+, SDIO, CE-ATA, SLC and MLC NAND. Antioch further enables new usage models by allowing USB to directly connect to a storage device independent of the main processor. Antioch is primarily targeted at handsets, to enable high speed connectivity to a PC through USB, and support for the latest mass storage devices. Antioch can, for instance, enable a multimedia phone to support HDD or NAND MLC storage, with the ability to download multimedia data at high speed from a PC directly to the storage device. SLIM Architecture The Simultaneous Link to Independent Multimedia SLIM architecture allows three interfaces P-port, S-port, and U-port to connect to one another independent of each other. With this architecture, connecting the device using Antioch to a PC through USB does not disturb any of the functions of the device, which can still access mass storage, at the same time the PC is synchronizing with the main processor. The SLIM architecture enables new usage models, in which a PC can access a mass storage device independent of the main processor, or enumerate access to both the mass storage and the main processor at the same time. In a handset, this enables to use the phone as a thumb drive or download media files to the phone while still having full functionality available on the phone. It also allows using the same phone as a modem to connect the PC to the web. Mass Storage Support S-Port The S-Port can be configured in two different modes, either simultaneously supporting an SDIO/MMC+/CE-ATA port and a x 8 NAND port, or supporting a unique x 16 NAND access port. Antioch, as part of its mass storage management functions, can fully manage a NAND device. An embedded 8051 manages the actual reading and writing of the NAND, along with its required protocols, including Single Level Cell SLC and Multi-Level Cell MLC NAND. It performs standard NAND management functions such as ECC and wear leveling. Processor Interface P-Port Communication with the external processor is realized through a dedicated processor interface. This interface supports both synchronous and asynchronous SRAM-mapped memory accesses. This ensures straightforward electrical communications with the processor, which may also have other devices connected on a shared memory bus. The memory address is decoded to access any of the multiple endpoint buffers inside Antioch. These endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the USB port. The processor writes and reads into these buffers via the memory interface. Access to these buffers is controlled by either using a DMA protocol or an interrupt to the main processor. These two modes are configurable by the external processor. As a DMA slave, Antioch generates a DMA request signal to signify to the main processor that a specific buffer is ready to be read from or written to. The external processor monitors this signal and polls Antioch for the specific buffers ready for read or write. It then performs the appropriate read or write operations on the buffer through the processor interface. This way, the external processor only deals with the buffers to access a multitude of storage devices connected to Antioch. In the Interrupt mode, Antioch communicates important buffer status changes to the external processor using an interrupt signal. The external processor then polls Antioch for the specific buffers ready for read or write, and it performs the appropriate read or write operations via the processor interface. Configuration The West Bridge Antioch device includes configuration and status registers that are accessible as memory-mapped registers through the processor interface. The configuration registers allow the system to specify certain behavior of Antioch. For example, it can mask certain status registers from raising an interrupt. The status registers convey various status of Antioch, such as the addresses of buffers for read operations. Ordering Information Ordering Code Turbo-MTP Enabled Package Type Available Clock Input Frequencies MHz CYWB0124AB-BVXI 100 VFBGA Pb-free 24, 26, 48 CYWB0125AB-BVXI 100 VFBGA Pb-free 24, 26, 48 CYWB0124ABX-FDXI WLCSP Pb-free 24, 26, 48 CYWB0125ABX-FDXI WLCSP Pb-free 24, 26, 48 This table contains advance information. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY WB 012 X AB X - XX X I Temperature Range I = Industrial Pb-free Package Type XX = BV or FD BV = 100-ball VFBGA FD = WLCSP X = CSP blank = BGA A generation Turbo MTP is enabled X = 4 or 5 4 = No 5 = Yes Antioch Bridge Family West Bridge Company ID CY = Cypress Page 5 of 9 [+] Feedback Package Diagram ADVANCE INFORMATION CYWB012X Family Figure 100-pin VFBGA 6 x 6 x mm BZ100A 51-85209 D Page 6 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family Acronyms Acronym direct memory access error correction codes hard disk drive input/output media transfer protocol multimedia card phase locked loop SLIM simultaneous link to independent media single level cell universal serial bus VFBGA very fine-pitch ball grid array WLCSP wafer level chip scale package CE-ATA consumer electronics-advanced technology attachment Document Conventions Units of Measure Symbol Mbps MHz mm V Unit of Measure Mega bytes per second Mega Hertz milli meter Volts Page 7 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family Document History Page Document Title CYWB012X Family, West Antioch Document Number 001-05898 B 2763925 OGC/AESA 09/15/09 Added Ordering Information table *C 3282406 06/14/2011 Added Ordering Code Definitions. Updated Package Diagram. Added Acronyms and Units of Measure. Updated in new template. Page 8 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 9 of 9 West Bridge and SLIM are registered trademarks and Antioch is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

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ADVANCE INFORMATION

CYWB012X Family

West Antioch

West Antioch
• architecture, allowing simultaneous and independent data paths between processor and USB, and between USB and mass storage
• High speed USB at 480 Mbps USB compliant Integrated USB transceiver, smart Serial Interface Engine 16 programmable endpoints
• Mass storage device support MMC/MMC+/SD NAND Flash x 8 or x 16, SLC Full NAND management ECC, wear-leveling
• Memory-mapped interface to main processor
• DMA slave support
• Ultra low power, V core operation
• Small footprint, 6 x 6 mm VFBGA and WLCSP
• Selectable clock input frequencies MHz, 24 MHz, 48 MHz
• Expanded mass storage device support MMC/MMC+/SD CE-ATA for micro-HDD NAND Flash x 8 or x 16, SLC Full NAND management ECC, wear-leveling
• Expanded selectable clock input frequencies MHz, 24 MHz, 26 MHz, 48 MHz
• Cellular Phones
• Portable Media Players
• Personal Digital Assistants
• Digital Cameras
• Portable Video Recorder

Logic Block Diagram

West Bridge Antioch Control Registers 8051 MCU

Access Control

Processor Interface High-Speed USB XCVR

SLIMTM

Mass Storage Interface

SD/MMC/CE-ATA

NAND
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

ADVANCE INFORMATION

CYWB012X Family

West Antioch is a peripheral mass storage controller that enhances a processor system with flexible mass storage support and high speed USB connectivity. Antioch has three different ports that enable connections among a main processor P-Port , one or more mass storage devices S-Port , and a USB host U-Port . Antioch’s unique SLIM architecture allows these three ports to interact simultaneously and independently of each other. This offers connectivity from USB to Storage typically used for PC high speed data download , from USB to Processor used for synchronization operations , and from Processor to Storage. Connected as a slave to a main processor, Antioch adds support for high speed USB and mass storage access including MMC, MMC+, SDIO, CE-ATA, SLC and MLC NAND. Antioch further enables new usage models by allowing USB to directly connect to a storage device independent of the main processor. Antioch is primarily targeted at handsets, to enable high speed connectivity to a PC through USB, and support for the latest mass storage devices. Antioch can, for instance, enable a multimedia phone to support HDD or NAND MLC storage, with the ability to download multimedia data at high speed from a PC directly to the storage device.

SLIM Architecture

The Simultaneous Link to Independent Multimedia SLIM architecture allows three interfaces P-port, S-port, and U-port to connect to one another independent of each other. With this architecture, connecting the device using Antioch to a PC through USB does not disturb any of the functions of the device, which can still access mass storage, at the same time the PC is synchronizing with the main processor. The SLIM architecture enables new usage models, in which a PC can access a mass storage device independent of the main processor, or enumerate access to both the mass storage and the main processor at the same time. In a handset, this enables to use the phone as a thumb drive or download media files to the phone while still having full functionality available on the phone. It also allows using the same phone as a modem to connect the PC to the web.

Mass Storage Support S-Port

The S-Port can be configured in two different modes, either simultaneously supporting an SDIO/MMC+/CE-ATA port and a x 8 NAND port, or supporting a unique x 16 NAND access port. Antioch, as part of its mass storage management functions, can fully manage a NAND device. An embedded 8051 manages the
actual reading and writing of the NAND, along with its required protocols, including Single Level Cell SLC and Multi-Level Cell MLC NAND. It performs standard NAND management functions such as ECC and wear leveling.

Processor Interface P-Port

Communication with the external processor is realized through a dedicated processor interface. This interface supports both synchronous and asynchronous SRAM-mapped memory accesses. This ensures straightforward electrical communications with the processor, which may also have other devices connected on a shared memory bus. The memory address is decoded to access any of the multiple endpoint buffers inside Antioch. These endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the USB port. The processor writes and reads into these buffers via the memory interface. Access to these buffers is controlled by either using a DMA protocol or an interrupt to the main processor. These two modes are configurable by the external processor. As a DMA slave, Antioch generates a DMA request signal to signify to the main processor that a specific buffer is ready to be read from or written to. The external processor monitors this signal and polls Antioch for the specific buffers ready for read or write. It then performs the appropriate read or write operations on the buffer through the processor interface. This way, the external processor only deals with the buffers to access a multitude of storage devices connected to Antioch. In the Interrupt mode, Antioch communicates important buffer status changes to the external processor using an interrupt signal. The external processor then polls Antioch for the specific buffers ready for read or write, and it performs the appropriate read or write operations via the processor interface.

Configuration

The West Bridge Antioch device includes configuration and status registers that are accessible as memory-mapped registers through the processor interface. The configuration registers allow the system to specify certain behavior of Antioch. For example, it can mask certain status registers from raising an interrupt. The status registers convey various status of Antioch, such as the addresses of buffers for read operations.
Ordering Information
Ordering Code

Turbo-MTP Enabled

Package Type

Available Clock Input Frequencies MHz

CYWB0124AB-BVXI
100 VFBGA Pb-free
24, 26, 48

CYWB0125AB-BVXI
100 VFBGA Pb-free
24, 26, 48

CYWB0124ABX-FDXI

WLCSP Pb-free
24, 26, 48

CYWB0125ABX-FDXI

WLCSP Pb-free
24, 26, 48

This table contains advance information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions

CY WB 012 X AB X - XX X I

Temperature Range I = Industrial Pb-free Package Type XX = BV or FD BV = 100-ball VFBGA FD = WLCSP X = CSP blank = BGA A generation Turbo MTP is enabled X = 4 or 5 4 = No 5 = Yes Antioch Bridge Family West Bridge Company ID CY = Cypress

Page 5 of 9
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Package Diagram

ADVANCE INFORMATION

CYWB012X Family

Figure 100-pin VFBGA 6 x 6 x mm BZ100A
51-85209 *D

Page 6 of 9
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ADVANCE INFORMATION

CYWB012X Family

Acronyms

Acronym
direct memory access
error correction codes
hard disk drive
input/output
media transfer protocol
multimedia card
phase locked loop

SLIM
simultaneous link to independent media
single level cell
universal serial bus

VFBGA very fine-pitch ball grid array

WLCSP wafer level chip scale package

CE-ATA
consumer electronics-advanced technology attachment

Document Conventions

Units of Measure

Symbol Mbps MHz mm V

Unit of Measure Mega bytes per second Mega Hertz milli meter Volts

Page 7 of 9
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ADVANCE INFORMATION

CYWB012X Family

Document History Page

Document Title CYWB012X Family, West Antioch Document Number 001-05898
*B 2763925 OGC/AESA 09/15/09 Added Ordering Information table
*C 3282406
06/14/2011
Added Ordering Code Definitions. Updated Package Diagram. Added Acronyms and Units of Measure. Updated in new template.

Page 8 of 9
[+] Feedback

ADVANCE INFORMATION

CYWB012X Family

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 9 of 9

West Bridge and SLIM are registered trademarks and Antioch is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYWB0125AB-BVXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CYWB0125AB-BVXI 508259