CY62167DV30LL-45ZXI

CY62167DV30LL-45ZXI Datasheet

CY62167DV30

Part	Datasheet
CY62167DV30LL-45ZXI	CY62167DV30LL-45ZXI (pdf)

Related Parts	Information
CY62167DV30LL-45ZXIT	CY62167DV30LL-45ZXIT

PDF Datasheet Preview
CY62167DV30 16-Mbit 1M x 16 Static RAM • TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM • Very high speed 45 ns • Wide voltage range 2.2V 3.6V • Ultra-low active power Typical active current 2 mA f = 1 MHz Typical active current mA f = fMax 45 ns speed • Ultra-low standby power • Easy memory expansion with CE1, CE2 and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free and non Pb-free 48-ball VFBGA and 48-pin TSOP I package Functional Description[1] The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device Logic Block Diagram A8 A7 DATA IN DRIVERS 1M x 16 / 2M x 8 RAM Array also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE1HIGH or CE2 LOW , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH , or during a Write operation CE1 LOW, CE2 HIGH and WE LOW . Writing to the device is accomplished by taking Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A19 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A19 . Reading from the device is accomplished by taking Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. ROW DECODER A11 A12 A13 A14 A15 A16 AA1187 A19 SENSE AMPS COLUMN DECODER Power-Down Circuit BYTE CE1 OE CE2 CE1 Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 CY62167DV30 Product Portfolio Product CY62167DV30LL VCC Range V Min. Typ.[2] Max. Pin Configuration[3, 4, 5] Speed ns Power Dissipation Operating ICC mA f = 1MHz Typ.[2] Max. f = fMax Typ.[2] Max. Standby ISB2 µA Typ.[2] Max. 48-ball VFBGA Top View 12 34 56 BLE OE A0 A1 A2 CE2 I/O8 BHE A3 A4 CE1 I/O0 Ordering Information Speed ns Ordering Code Package Diagram Package Type 45 CY62167DV30LL-45ZXI 51-85183 48-pin TSOP I 12 x 1 mm Pb-free 55 CY62167DV30LL-55BVI 51-85178 48-ball Fine Pitch BGA 8 x 1 mm CY62167DV30LL-55BVXI 48-ball Fine Pitch BGA 8 x 1 mm Pb-free CY62167DV30LL-55ZI 51-85183 48-pin TSOP I 12 x 1 mm CY62167DV30LL-55ZXI 48-pin TSOP I 12 x 1 mm Pb-free 70 CY62167DV30LL-70BVI 51-85178 48-ball Fine Pitch BGA 8 x 1 mm Please contact your local Cypress sales representative for availability of these parts Package Diagrams Operating Range Industrial 48-ball VFBGA 8 x 1 mm 51-85178 TOP VIEW A1 CORNER 12 3 4 5 6 A B C D E F G H BOTTOM VIEW M C M C A B Ø0.30±0.05 48X A1 CORNER 6 54 3 2 1 A B C D E F G H C MAX. SEATING PLANE C B 0.15 4X MAX. 51-85178-** Page 10 of 12 CY62167DV30 Package Diagrams continued 48-pin TSOP I 12 x 1mm 51-85183 DIMENSIONS IN INCHES[MM] MIN. JEDEC # MO-142 MAX. TYP. 0°-5° MAX. SEATING PLANE GAUGE PLANE Ordering Information table from BV48A to BV48B 304054 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #12 on page #4 Added Pb-free packages on page # 10 492895 See ECN VKN Modified datasheet to explain x8 configurability Removed L power bin from the product offering Updated Ordering Information Table Page 12 of 12

PDF Datasheet Preview

CY62167DV30
16-Mbit 1M x 16 Static RAM
• TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM
• Very high speed 45 ns
• Wide voltage range 2.2V 3.6V
• Ultra-low active power

Typical active current 2 mA f = 1 MHz Typical active current mA f = fMax 45 ns
speed
• Ultra-low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball VFBGA
and 48-pin TSOP I package

Functional Description[1]

The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device

Logic Block Diagram

A8 A7

DATA IN DRIVERS
1M x 16 / 2M x 8 RAM Array
also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE1HIGH or CE2 LOW , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH , or during a Write operation CE1 LOW, CE2 HIGH and WE LOW . Writing to the device is accomplished by taking Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A19 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A19 . Reading from the device is accomplished by taking Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes.

ROW DECODER A11 A12 A13 A14 A15 A16 AA1187 A19

SENSE AMPS

COLUMN DECODER

Power-Down

Circuit

BYTE

CE1 OE

CE2 CE1

Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

CY62167DV30

Product Portfolio

Product CY62167DV30LL

VCC Range V

Min.

Typ.[2]

Max.

Pin Configuration[3, 4, 5]

Speed ns

Power Dissipation

Operating ICC mA
f = 1MHz Typ.[2] Max.
f = fMax Typ.[2] Max.

Standby ISB2 µA Typ.[2] Max.
48-ball VFBGA Top View
12 34 56

BLE OE A0 A1 A2 CE2

I/O8 BHE A3 A4 CE1 I/O0
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type
45 CY62167DV30LL-45ZXI 51-85183 48-pin TSOP I 12 x 1 mm Pb-free
55 CY62167DV30LL-55BVI 51-85178 48-ball Fine Pitch BGA 8 x 1 mm

CY62167DV30LL-55BVXI
48-ball Fine Pitch BGA 8 x 1 mm Pb-free

CY62167DV30LL-55ZI
51-85183 48-pin TSOP I 12 x 1 mm

CY62167DV30LL-55ZXI
48-pin TSOP I 12 x 1 mm Pb-free
70 CY62167DV30LL-70BVI 51-85178 48-ball Fine Pitch BGA 8 x 1 mm

Please contact your local Cypress sales representative for availability of these parts

Package Diagrams

Operating Range

Industrial
48-ball VFBGA 8 x 1 mm 51-85178

TOP VIEW

A1 CORNER 12 3 4 5 6

A B C D E F G H

BOTTOM VIEW

M C M C A B Ø0.30±0.05 48X

A1 CORNER
6 54 3 2 1

A B C D E F G H

C MAX.

SEATING PLANE C

B 0.15 4X

MAX.
51-85178-**

Page 10 of 12

CY62167DV30

Package Diagrams continued
48-pin TSOP I 12 x 1mm 51-85183

DIMENSIONS IN INCHES[MM] MIN. JEDEC # MO-142

MAX.

TYP.
0°-5°

MAX.

SEATING PLANE

GAUGE PLANE
Ordering Information table from BV48A to BV48B
304054 See ECN
PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables

Added Footnote #12 on page #4

Added Pb-free packages on page # 10
492895 See ECN VKN Modified datasheet to explain x8 configurability

Removed L power bin from the product offering
Updated Ordering Information Table

Page 12 of 12

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Datasheet ID: CY62167DV30LL-45ZXI 507824