CY62137FV30LL-45BVIT

CY62137FV30LL-45BVIT Datasheet

CY62137FV30

Part	Datasheet
CY62137FV30LL-45BVIT	CY62137FV30LL-45BVIT (pdf)

Related Parts	Information
CY62137FV30LL-45BVI	CY62137FV30LL-45BVI

PDF Datasheet Preview
CY62137FV30 2-Mbit 128 K x 16 Static RAM 2-Mbit 128 K x 16 Static RAM • Very high speed 45 ns • Temperature ranges Industrial °C to +85 °C • Wide voltage range V • Pin compatible with CY62137CV/CV25/CV30/CV33, CY62137V, and CY62137EV30 • Ultra low standby power Typical standby current 1 Maximum standby current 5 Industrial • Ultra low active power Typical active current mA at f = 1 MHz 45 ns speed • Easy memory expansion with CE and OE features • Automatic power down when deselected • Complementary metal oxide semiconductor CMOS for optimum speed and power • Byte power down feature • Available in Pb free 48-ball very fine-pitch ball grid array VFBGA and 44-pin thin small outline package TSOP II package Functional Description The CY62137FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected CE HIGH or both BLE and BHE are HIGH . The input and output pins I/O0 through I/O15 are placed in a high impedance state in the following conditions when the device is deselected CE HIGH , the outputs are disabled OE HIGH , both the Byte High Enable and the Byte Low Enable are disabled BHE, BLE HIGH , or during an active write operation CE LOW and WE LOW . Write to the device by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 is written into the location specified on the address pins A0 through A16 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A16 . Read from the device by taking Chip Enable CE and Output Enable OE LOW, while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of read and write modes. ROW DECODER A11 A12 A13 A14 A15 A16 SENSE AMPS Logic Block Diagram A10 A9 A8 A7 AA65 A4 A3 A2 A1 A0 POWER DOWN CIRCUIT DATA IN DRIVERS 128K x 16 RAM Array COLUMN DECODER CE BHE BLE BHE WE CE OE BLE • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY62137FV30 Contents Product Portfolio 3 Pin Configuration 3 Maximum Ratings 4 Operating Range 4 Electrical Characteristics 4 Capacitance 5 Thermal Resistance 5 AC Test Loads and Waveforms 5 Data Retention Characteristics 6 Data Retention Waveform 6 Switching Characteristics 7 Switching Waveforms 8 Truth Table 11 Ordering Information 12 Ordering Code Definitions 12 Package Diagrams 13 Acronyms 14 Document Conventions 14 Units of Measure 14 Document History Page 15 Sales, Solutions, and Legal Information 16 Worldwide Sales and Design Support 16 Products 16 PSoC Solutions 16 Page 2 of 16 [+] Feedback CY62137FV30 Product Portfolio Product Range VCC Range V Min CY62137FV30LL Industrial V Typ [1] V Max V Speed ns 45 Power Dissipation Operating ICC mA f = 1MHz Typ [1] Max f = fmax Typ [1] Max Standby ISB2 Typ [1] Max Pin Configuration Figure 48-Ball VFBGA Pinout [2, 3] BLE OE A0 A1 A2 NC I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC VCC I/O12 NC A16 I/O4 VSS I/O14 I/O13 A14 A15 I/O5 I/O6 I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC Figure 44-Pin TSOP II [2] A3 2 A2 3 A1 4 A0 5 I/O0 7 I/O1 8 I/O2 9 I/O3 10 VCC 11 VSS 12 I/O4 13 I/O5 14 I/O6 15 I/O7 16 WE 17 AA1165 18 19 A14 20 A13 21 A12 22 44 A5 43 A6 42 A7 41 OE 40 BHE 39 BLE Ordering Information Speed ns 45 Ordering Code CY62137FV30LL-45BVI CY62137FV30LL-45BVXI CY62137FV30LL-45ZSXI Package Diagram Package Type 51-85150 48-ball VFBGA 48-ball VFBGA Pb-free 51-85087 44-pin TSOP II Pb-free Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 3 7 F V30 LL - 45 XX X I Temperature Grade I = Industrial Pb-free Package Type XX = BV or ZS BV = 48-ball VFBGA ZS = 44-pin TSOP II Speed Grade 45 ns Low Power Voltage Range 3 V typical Process Technology 90 nm Bus width = x 16 Density = 2-Mbit Family Code MoBL SRAM family Company ID CY = Cypress Operating Range Industrial Page 12 of 16 [+] Feedback CY62137FV30 Package Diagrams Figure 48-ball VFBGA 6 x 8 x mm BV48/BZ48, 51-85150 51-85150 F Page 13 of 16 [+] Feedback CY62137FV30 Package Diagrams continued Figure 44-pin TSOP Z44-II, 51-85087 PIN 1 I.D. TOP VIEW BOTTOM VIEW ZZZ ZXZ EJECTOR MARK OPTIONAL CAN BE LOCATED ANYWHERE IN THE BOTTOM PKG DIMENSION IN MM INCH MAX MIN. BASE PLANE SEATING PLANE 0°-5° 51-85087-C Acronyms Acronym byte low enable byte high enable chip enable CMOS complementary metal oxide semiconductor input/output output enable SRAM static random access memory TSOP thin small outline package VFBGA very fine-pitch ball grid array write enable Document Conventions Updated Ordering Information Table Added footnote 13 related to tACE D 901800 See ECN Added footnote 9 related to ISB2 and ICCDR Made footnote 14 applicable to AC parameters from tACE E 1371124 See ECN VKN/AESA Converted Automotive information from preliminary to final Changed IIX min spec from to and IIX max spec from +1 to +4 Changed IOZ min spec from to and IOZ max spec from +1 to +4 F 1875374 See ECN VKN/AESA Added -45BVI part in the Ordering Information table G 2943752 06/03/2010 Added Contents Added footnote related to Chip enable and Byte enables in Truth Table Updated Package Diagrams Updated links in Sales, Solutions, and Legal Information H 3055031 10/12/10 RAME Added Acronyms and Units of Measure Table Converted all table notes into footnotes. Updated Electrical Characteristics, Switching Characteristics table, and Data Retention Characteristics table Updated Package Diagrams from 51-85150 E to F Changed ISB1/ISB2/ICCDR test conditions to reflect byte power down feature I 3123998 01/03/2011 RAME Separated Automotive and Industrial parts from datasheet Removed Automotive info *J 3285093 06/16/2011 RAME Updated Functional Description Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.” . Updated in new template. Page 15 of 16 [+] Feedback CY62137FV30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 16 of 16 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY62137FV30
2-Mbit 128 K x 16 Static RAM
2-Mbit 128 K x 16 Static RAM
• Very high speed 45 ns
• Temperature ranges

Industrial °C to +85 °C
• Wide voltage range V
• Pin compatible with CY62137CV/CV25/CV30/CV33,

CY62137V, and CY62137EV30
• Ultra low standby power

Typical standby current 1 Maximum standby current 5 Industrial
• Ultra low active power Typical active current mA at f = 1 MHz 45 ns speed
• Easy memory expansion with CE and OE features
• Automatic power down when deselected
• Complementary metal oxide semiconductor CMOS for optimum speed and power
• Byte power down feature
• Available in Pb free 48-ball very fine-pitch ball grid array VFBGA and 44-pin thin small outline package TSOP II package

Functional Description

The CY62137FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected CE HIGH or both BLE and BHE are HIGH . The input and output pins I/O0 through I/O15 are placed in a high impedance state in the following conditions when the device is deselected CE HIGH , the outputs are disabled OE HIGH , both the Byte High Enable and the Byte Low Enable are disabled BHE, BLE HIGH , or during an active write operation CE LOW and WE LOW .

Write to the device by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 is written into the location specified on the address pins A0 through A16 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A16 .

Read from the device by taking Chip Enable CE and Output Enable OE LOW, while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of read and write modes.

ROW DECODER A11 A12 A13 A14 A15 A16

SENSE AMPS

Logic Block Diagram

A10 A9 A8 A7 AA65 A4 A3 A2 A1 A0

POWER DOWN CIRCUIT

DATA IN DRIVERS
128K x 16 RAM Array

COLUMN DECODER

CE BHE BLE

BHE WE CE OE BLE
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY62137FV30

Contents

Product Portfolio 3 Pin Configuration 3 Maximum Ratings 4 Operating Range 4 Electrical Characteristics 4 Capacitance 5 Thermal Resistance 5 AC Test Loads and Waveforms 5 Data Retention Characteristics 6 Data Retention Waveform 6 Switching Characteristics 7 Switching Waveforms 8
Truth Table 11 Ordering Information 12
Ordering Code Definitions 12 Package Diagrams 13 Acronyms 14 Document Conventions 14

Units of Measure 14 Document History Page 15 Sales, Solutions, and Legal Information 16

Worldwide Sales and Design Support 16 Products 16 PSoC Solutions 16

Page 2 of 16 [+] Feedback

CY62137FV30

Product Portfolio

Product

Range

VCC Range V

Min CY62137FV30LL Industrial V

Typ [1] V

Max V

Speed ns 45

Power Dissipation

Operating ICC mA
f = 1MHz Typ [1] Max
f = fmax Typ [1] Max

Standby ISB2 Typ [1] Max

Pin Configuration

Figure 48-Ball VFBGA Pinout [2, 3]

BLE OE A0 A1 A2 NC

I/O8 BHE A3 A4 CE I/O0 B

I/O9 I/O10 A5 A6 I/O1 I/O2 C

VSS I/O11 NC A7 I/O3 VCC

VCC I/O12 NC A16 I/O4 VSS

I/O14 I/O13 A14 A15 I/O5 I/O6

I/O15 NC A12 A13 WE I/O7 G

NC A8 A9 A10 A11 NC

Figure 44-Pin TSOP II [2]

A3 2 A2 3 A1 4 A0 5

I/O0 7 I/O1 8 I/O2 9 I/O3 10 VCC 11 VSS 12 I/O4 13 I/O5 14 I/O6 15 I/O7 16

WE 17

AA1165
18 19

A14 20

A13 21

A12 22
44 A5 43 A6 42 A7
41 OE
40 BHE
39 BLE
Ordering Information

Speed ns 45
Ordering Code CY62137FV30LL-45BVI CY62137FV30LL-45BVXI CY62137FV30LL-45ZSXI

Package Diagram

Package Type
51-85150 48-ball VFBGA
48-ball VFBGA Pb-free
51-85087 44-pin TSOP II Pb-free

Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions

CY 621 3 7 F V30 LL - 45 XX X I

Temperature Grade I = Industrial Pb-free Package Type XX = BV or ZS BV = 48-ball VFBGA ZS = 44-pin TSOP II Speed Grade 45 ns Low Power Voltage Range 3 V typical Process Technology 90 nm Bus width = x 16 Density = 2-Mbit Family Code MoBL SRAM family Company ID CY = Cypress

Operating Range

Industrial

Page 12 of 16 [+] Feedback

CY62137FV30

Package Diagrams

Figure 48-ball VFBGA 6 x 8 x mm BV48/BZ48, 51-85150
51-85150 *F

Page 13 of 16 [+] Feedback

CY62137FV30

Package Diagrams continued

Figure 44-pin TSOP Z44-II, 51-85087

PIN 1 I.D.

TOP VIEW

BOTTOM VIEW

ZZZ ZXZ

EJECTOR MARK OPTIONAL

CAN BE LOCATED ANYWHERE IN THE BOTTOM PKG

DIMENSION IN MM INCH MAX MIN.

BASE PLANE

SEATING PLANE
0°-5°
51-85087-*C

Acronyms

Acronym
byte low enable
byte high enable
chip enable

CMOS
complementary metal oxide semiconductor
input/output
output enable

SRAM
static random access memory

TSOP
thin small outline package

VFBGA very fine-pitch ball grid array
write enable

Document Conventions
Updated Ordering Information Table

Added footnote 13 related to tACE
*D 901800 See ECN

Added footnote 9 related to ISB2 and ICCDR Made footnote 14 applicable to AC parameters from tACE
*E 1371124 See ECN VKN/AESA Converted Automotive information from preliminary to final

Changed IIX min spec from to and IIX max spec from +1 to +4 Changed IOZ min spec from to and IOZ max spec from +1 to +4
*F 1875374 See ECN VKN/AESA Added -45BVI part in the Ordering Information table
*G 2943752 06/03/2010

Added Contents Added footnote related to Chip enable and Byte enables in Truth Table Updated Package Diagrams Updated links in Sales, Solutions, and Legal Information
*H 3055031 10/12/10 RAME Added Acronyms and Units of Measure Table Converted all table notes into footnotes. Updated Electrical Characteristics, Switching Characteristics table, and Data Retention Characteristics table Updated Package Diagrams from 51-85150 *E to *F Changed ISB1/ISB2/ICCDR test conditions to reflect byte power down feature
*I 3123998 01/03/2011 RAME Separated Automotive and Industrial parts from datasheet Removed Automotive info
*J 3285093 06/16/2011 RAME Updated Functional Description Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.” . Updated in new template.

Page 15 of 16 [+] Feedback

CY62137FV30

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 16 of 16

MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62137FV30LL-45BVIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY62137FV30LL-45BVIT 507811