CY62136VNLL-70ZSXE

CY62136VNLL-70ZSXE Datasheet

CY62136VN

Part	Datasheet
CY62136VNLL-70ZSXE	CY62136VNLL-70ZSXE (pdf)

Related Parts	Information
CY62136VNLL-70ZSXET	CY62136VNLL-70ZSXET
CY62136VNLL-55ZSXAT	CY62136VNLL-55ZSXAT
CY62136VNLL-70BAXA	CY62136VNLL-70BAXA
CY62136VNLL-70BAXAT	CY62136VNLL-70BAXAT
CY62136VNLL-70ZSXA	CY62136VNLL-70ZSXA
CY62136VNLL-70ZSXAT	CY62136VNLL-70ZSXAT
CY62136VNLL-55ZSXA	CY62136VNLL-55ZSXA

PDF Datasheet Preview
CY62136VN 2-Mbit 128K x 16 Static RAM ROW DECODER A11 A12 A13 A14 A15 A16 SENSE AMPS • Temperature Ranges Industrial to 85°C Automotive-A to 85°C Automotive-E to 125°C • High speed 55 ns • Wide voltage range • Ultra-low active, standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • CMOS for optimum speed/power • Available in standard Pb-free 44-pin TSOP Type II, Pb-free and non Pb-free 48-ball FBGA packages Functional Description[1] The CY62136VN is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 128K x 16 RAM Array A2 A1 A0 COLUMN DECODER portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected CE HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE LOW, and WE LOW . Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A16 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A16 . Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. I/O0 I/O7 I/O8 I/O15 BHE WE CE OE BLE PinConfigurations[3] TSOP II Forward Top View A4 1 A3 2 A2 3 A1 4 A0 5 CE 6 I/O 0 7 I/O 1 8 I/O 2 9 I/O 3 10 VCC 11 VSS 12 I/O 4 13 I/O 5 14 I/O 6 15 I/O 7 16 WE 17 A16 18 A15 19 A14 20 A13 21 A12 22 44 A5 43 A6 42 A7 41 OE 40 BHE 39 BLE 38 I/O 15 37 I/O 14 36 I/O 13 35 I/O 12 34 VSS 33 VCC 32 I/O 11 31 I/O 10 30 I/O 9 29 I/O 8 28 NC 27 A8 26 A9 25 A10 24 A11 23 NC Note For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY62136VN Product Portfolio Product CY62136VNLL VCC Range V Min Typ.[2] Max Pin Configurations[3] Speed 55 70 Ordering Information Speed ns Ordering Code Package Diagram Package Type 55 CY62136VNLL-55ZXI 51-85087 44-pin TSOP II Pb-Free CY62136VNLL-55BAI 51-85096 48-Ball mm x mm FBGA CY62136VNLL-55ZSXA 51-85087 44-pin TSOP II Pb-Free 70 CY62136VNLL-70ZXI 51-85087 44-pin TSOP II Pb-Free CY62136VNLL-70BAI 51-85096 48-Ball mm x mm FBGA CY62136VNLL-70BAXA 51-85096 48-Ball mm x mm FBGA Pb-Free CY62136VNLL-70ZSXA 51-85087 44-pin TSOP II Pb-Free CY62136VNLL-70ZSXE 51-85087 44-pin TSOP II Pb-Free Please contact your local Cypress sales representative for availability of these parts Package Diagrams 44-pin TSOP II 51-85087 Operating Range Industrial Automotive-A Industrial Automotive-A Automotive-E 51-85087-A Page 10 of 12 [+] Feedback CY62136VN Package Diagrams continued 48-Ball mm x mm FBGA 51-85096 TOP VIEW PIN 1 CORNER LASER MARK 12 3 4 5 6 A B C D E F G H BOTTOM VIEW M C M C A B Ø0.30±0.05 48X 6 54321 PIN 1 CORNER A B C D E F G H B 0.15 4X SEATING PLANE C MAX. 51-85096-F MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the products of their respective holders. Updated ordering Information table Page 12 of 12 [+] Feedback

PDF Datasheet Preview

CY62136VN
2-Mbit 128K x 16 Static RAM

ROW DECODER A11 A12 A13 A14 A15 A16

SENSE AMPS
• Temperature Ranges Industrial to 85°C Automotive-A to 85°C Automotive-E to 125°C
• High speed 55 ns
• Wide voltage range
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in standard Pb-free 44-pin TSOP Type II,

Pb-free and non Pb-free 48-ball FBGA packages

Functional Description[1]

The CY62136VN is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in

Logic Block Diagram

DATA IN DRIVERS

A10 A9

A8 A7
128K x 16

RAM Array

A2 A1 A0

COLUMN DECODER
portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected CE HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE LOW, and WE LOW .

Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A16 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A16 .

Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes.

I/O0 I/O7 I/O8 I/O15

BHE WE CE OE BLE

PinConfigurations[3]

TSOP II Forward Top View

A4 1 A3 2 A2 3 A1 4 A0 5 CE 6

I/O 0 7 I/O 1 8 I/O 2 9

I/O 3 10 VCC 11 VSS 12 I/O 4 13 I/O 5 14 I/O 6 15 I/O 7 16 WE 17

A16 18 A15 19 A14 20 A13 21 A12 22
44 A5 43 A6
42 A7 41 OE
40 BHE 39 BLE
38 I/O 15 37 I/O 14 36 I/O 13 35 I/O 12 34 VSS 33 VCC 32 I/O 11 31 I/O 10 30 I/O 9 29 I/O 8 28 NC 27 A8 26 A9 25 A10 24 A11 23 NC

Note For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY62136VN

Product Portfolio

Product CY62136VNLL

VCC Range V Min Typ.[2] Max

Pin Configurations[3]

Speed 55 70
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type
55 CY62136VNLL-55ZXI
51-85087 44-pin TSOP II Pb-Free

CY62136VNLL-55BAI
51-85096 48-Ball mm x mm FBGA

CY62136VNLL-55ZSXA 51-85087 44-pin TSOP II Pb-Free
70 CY62136VNLL-70ZXI
51-85087 44-pin TSOP II Pb-Free

CY62136VNLL-70BAI
51-85096 48-Ball mm x mm FBGA

CY62136VNLL-70BAXA 51-85096 48-Ball mm x mm FBGA Pb-Free

CY62136VNLL-70ZSXA 51-85087 44-pin TSOP II Pb-Free

CY62136VNLL-70ZSXE 51-85087 44-pin TSOP II Pb-Free

Please contact your local Cypress sales representative for availability of these parts

Package Diagrams
44-pin TSOP II 51-85087

Operating Range Industrial

Automotive-A Industrial

Automotive-A

Automotive-E
51-85087-*A

Page 10 of 12 [+] Feedback

CY62136VN

Package Diagrams continued
48-Ball mm x mm FBGA 51-85096

TOP VIEW

PIN 1 CORNER LASER MARK
12 3 4 5 6

A B C D E F G H

BOTTOM VIEW

M C M C A B Ø0.30±0.05 48X
6 54321

PIN 1 CORNER

A B C D E F G H

B 0.15 4X

SEATING PLANE C

MAX.
51-85096-*F

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the products of their respective holders.
Updated ordering Information table

Page 12 of 12 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62136VNLL-70ZSXE Datasheet file may be downloaded here without warranties.

Datasheet ID: CY62136VNLL-70ZSXE 507809