CY62128DV30LL-70ZI

CY62128DV30LL-70ZI Datasheet

CY62128DV30

Part	Datasheet
CY62128DV30LL-70ZI	CY62128DV30LL-70ZI (pdf)

Related Parts	Information
CY62128DV30LL-70ZXI	CY62128DV30LL-70ZXI
CY62128DV30LL-70SXI	CY62128DV30LL-70SXI
CY62128DV30LL-70SI	CY62128DV30LL-70SI
CY62128DV30LL-55SXI	CY62128DV30LL-55SXI

PDF Datasheet Preview
CY62128DV30 1-Mb 128K x 8 Static RAM • Very high speed 55 and 70 ns • Wide voltage range 2.2V to 3.6V • Pin compatible with CY62128V • Ultra-low active power Functional Description[1] The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device Logic Block Diagram also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 CE1 HIGH or Chip Enable 2 CE2 LOW. The input/output pins I/O0 through I/O7 are placed in a high-impedance state when deselected Chip Enable 1 CE1 HIGH or Chip Enable 2 CE2 LOW, outputs are disabled OE HIGH , or during a write operation Chip Enable 1 CE1 LOW and Chip Enable 2 CE2 HIGH and Write Enable WE LOW . Writing to the device is accomplished by taking Chip Enable 1 CE1 LOW with Chip Enable 2 CE2 HIGH and Write Enable WE LOW. Data on the eight I/O pins is then written into the location specified on the Address pin A0 through A16 . Reading from the device is accomplished by taking Chip Enable 1 CE1 LOW with Chip Enable 2 CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins I/Oo through I/O7 are placed in a high-impedance state when the device is deselected CE1 HIGH or CE2 LOW , the outputs are disabled OE HIGH or during a write operation CE1 LOW, CE2 HIGH , and WE LOW . A0 A1 A2 A3 A4 A5 A6 A7 AAA1089 A11 CE1 CE2 ROW DECODER SENSE AMPS Data in Drivers 128K x 8 ARRAY COLUMN DECODER Powerdown I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 A12 A 13 A 14 A 15 A 16 Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Pin Configurations[2] CY62128DV30 Top View SOIC DNU 1 A16 2 32 VCC A14 A12 A7 12 13 A14 3 A12 4 A7 5 A6 6 A5 7 30 CE2 29 WE A5 A4 14 15 16 28 A13 27 A8 26 A9 A4 8 A3 9 25 A11 24 OE A2 10 Ordering Information Speed ns Ordering Code 55 CY62128DV30L-55SI CY62128DV30LL-55SI CY62128DV30LL-55SXI CY62128DV30L-55ZI CY62128DV30LL-55ZI CY62128DV30LL-55ZXI CY62128DV30L-55ZAI CY62128DV30LL-55ZAI CY62128DV30LL-55ZAXI CY62128DV30L-55ZRI CY62128DV30LL-55ZRI CY62128DV30LL-55ZRXI 70 CY62128DV30L-70SI CY62128DV30LL-70SI CY62128DV30LL-70SXI CY62128DV30L-70ZI CY62128DV30LL-70ZI CY62128DV30LL-70ZXI CY62128DV30L-70ZAI CY62128DV30LL-70ZAI CY62128DV30LL-70ZAXI CY62128DV30L-70ZRI CY62128DV30LL-70ZRI Package Diagram Package Type 51-85081 32-lead SOIC 51-85081 32-lead SOIC 51-85081 32-lead SOIC Pb-Free 51-85056 32-lead TSOP Type 1 51-85056 32-lead TSOP Type 1 51-85056 32-lead TSOP Type 1 Pb-Free 51-85094 32-lead Small TSOP 51-85094 32-lead Small TSOP 51-85094 32-lead Small TSOP Pb-Free 51-85081 32-lead SOIC 51-85081 32-lead SOIC 51-85081 32-lead SOIC Pb-Free 51-85056 32-lead TSOP Type 1 51-85056 32-lead TSOP Type 1 51-85056 32-lead TSOP Type 1 Pb-Free Add 70-ns speed, updated ordering information 129002 08/29/03 CDY Changed Icc 1 MHz typ from mA to mA 347394 See ECN PCI Added Lead-Free Packages in Ordering Information Table 395936 See ECN SYT Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Corrected CE1 and CE2 waveforms on Write Cycle No.1 on Page# Edited the Write Cycle No.1 switching waveform Data I/O to include Don’t Care Condition on Page# 6 Updated the ordering information on Page # 8 428906 See ECN AJU Added Thermal Resistance numbers for RTSOP package Updated Ordering Information table by replacing Package Name column with Package Diagram 464721 See ECN NXR Updated the Block Diagram on page # 1 470383 See ECN NXR Changed pin# 1 of SOIC and STSOP I, pin # 9 of TSOP I and RTSOP I from NC to DNU and added footnote# 3 Page 11 of 11 [+] Feedback

PDF Datasheet Preview

CY62128DV30
1-Mb 128K x 8 Static RAM
• Very high speed 55 and 70 ns
• Wide voltage range 2.2V to 3.6V
• Pin compatible with CY62128V
• Ultra-low active power

Functional Description[1]

The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device

Logic Block Diagram
also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 CE1 HIGH or Chip Enable 2 CE2 LOW. The input/output pins I/O0 through I/O7 are placed in a high-impedance state when deselected Chip Enable 1 CE1 HIGH or Chip Enable 2 CE2 LOW, outputs are disabled OE HIGH , or during a write operation Chip Enable 1 CE1 LOW and Chip Enable 2 CE2 HIGH and Write Enable WE LOW .

Writing to the device is accomplished by taking Chip Enable 1 CE1 LOW with Chip Enable 2 CE2 HIGH and Write Enable WE LOW. Data on the eight I/O pins is then written into the location specified on the Address pin A0 through A16 .

Reading from the device is accomplished by taking Chip Enable 1 CE1 LOW with Chip Enable 2 CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins I/Oo through I/O7 are placed in a high-impedance state when the device is deselected CE1 HIGH or CE2 LOW , the outputs are disabled OE HIGH or during a write operation CE1 LOW, CE2 HIGH , and WE LOW .

A0 A1 A2 A3 A4 A5 A6 A7 AAA1089 A11

CE1 CE2

ROW DECODER SENSE AMPS

Data in Drivers
128K x 8 ARRAY

COLUMN DECODER

Powerdown

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

A12 A 13 A 14 A 15 A 16

Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Pin Configurations[2]

CY62128DV30

Top View

SOIC

DNU 1 A16 2
32 VCC A14

A12 A7
12 13

A14 3 A12 4

A7 5 A6 6 A5 7
30 CE2 29 WE

A5 A4
14 15 16
28 A13
27 A8
26 A9

A4 8 A3 9
25 A11 24 OE

A2 10
Ordering Information

Speed ns
Ordering Code
55 CY62128DV30L-55SI

CY62128DV30LL-55SI

CY62128DV30LL-55SXI

CY62128DV30L-55ZI

CY62128DV30LL-55ZI

CY62128DV30LL-55ZXI

CY62128DV30L-55ZAI

CY62128DV30LL-55ZAI

CY62128DV30LL-55ZAXI

CY62128DV30L-55ZRI

CY62128DV30LL-55ZRI

CY62128DV30LL-55ZRXI
70 CY62128DV30L-70SI

CY62128DV30LL-70SI

CY62128DV30LL-70SXI

CY62128DV30L-70ZI

CY62128DV30LL-70ZI

CY62128DV30LL-70ZXI

CY62128DV30L-70ZAI

CY62128DV30LL-70ZAI

CY62128DV30LL-70ZAXI

CY62128DV30L-70ZRI

CY62128DV30LL-70ZRI

Package Diagram

Package Type
51-85081 32-lead SOIC
51-85081 32-lead SOIC
51-85081 32-lead SOIC Pb-Free
51-85056 32-lead TSOP Type 1
51-85056 32-lead TSOP Type 1
51-85056 32-lead TSOP Type 1 Pb-Free
51-85094 32-lead Small TSOP
51-85094 32-lead Small TSOP
51-85094 32-lead Small TSOP Pb-Free
51-85081 32-lead SOIC
51-85081 32-lead SOIC
51-85081 32-lead SOIC Pb-Free
51-85056 32-lead TSOP Type 1
51-85056 32-lead TSOP Type 1
51-85056 32-lead TSOP Type 1 Pb-Free
Add 70-ns speed, updated ordering information
129002 08/29/03 CDY Changed Icc 1 MHz typ from mA to mA
347394 See ECN
PCI Added Lead-Free Packages in Ordering Information Table
395936 See ECN SYT Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Corrected CE1 and CE2 waveforms on Write Cycle No.1 on Page# Edited the Write Cycle No.1 switching waveform Data I/O to include Don’t

Care Condition on Page# 6
Updated the ordering information on Page # 8
428906 See ECN AJU Added Thermal Resistance numbers for RTSOP package
Updated Ordering Information table by replacing Package Name column with

Package Diagram
464721 See ECN NXR Updated the Block Diagram on page # 1
470383 See ECN NXR Changed pin# 1 of SOIC and STSOP I, pin # 9 of TSOP I and RTSOP I from

NC to DNU and added footnote# 3

Page 11 of 11 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62128DV30LL-70ZI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY62128DV30LL-70ZI 507806